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driver/src/hw3/cpu.c

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+/****************************************************************************
+
+Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
+
+This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
+be copied by any method or incorporated into another program without
+the express written consent of Aerospace C.Power. This Information or any portion
+thereof remains the property of Aerospace C.Power. The Information contained herein
+is believed to be accurate and Aerospace C.Power assumes no responsibility or
+liability for its use in any way and conveys no license or title under
+any patent or copyright and makes no representation or warranty that this
+Information is free from patent or copyright infringement.
+
+****************************************************************************/
+/* os shim includes */
+#include "os_types.h"
+#include "hw_reg_api.h"
+#include "iot_system.h"
+#include "clk.h"
+#include "encoding.h"
+
+#define CPU_FRQ_FPGA    (75 * 1000 * 1000)
+#define cpu_read_csr(reg) ({ unsigned long __tmp; \
+  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __tmp; })
+
+cpu_state g_cpu1_state = {0};
+
+uint64_t IRAM_ATTR cpu_get_mcycle()
+{
+    int32_t mcycle = 0;
+    int32_t mcycleh = 0;
+    int32_t mcycle_later = 0;
+
+    asm volatile ("csrr %0, mcycleh" : "=r"(mcycleh));
+    asm volatile ("csrr %0, mcycle" : "=r"(mcycle));
+    asm volatile ("csrr %0, mcycleh" : "=r"(mcycle_later));
+
+    if (mcycle_later != mcycleh) {
+        asm volatile ("csrr %0, mcycle" : "=r"(mcycle));
+    }
+
+    return (uint64_t)(mcycle + ((uint64_t)mcycle_later << 32));
+}
+
+uint32_t IRAM_ATTR cpu_get_mhartid()
+{
+    uint32_t hartid = cpu_read_csr(mhartid);
+
+    return hartid;
+}
+
+uint32_t cpu_get_clock()
+{
+#if HW_PLATFORM == HW_PLATFORM_SILICON
+    uint32_t freq;
+
+    freq = clk_core_freq_get();
+
+    return freq;
+#else
+    return CPU_FRQ_FPGA;
+#endif
+}
+
+void IRAM_ATTR cpu_enable_irq(uint32_t mask)
+{
+    write_csr(mstatus, mask);
+}
+
+
+uint32_t IRAM_ATTR cpu_disable_irq(void)
+{
+    uint32_t mask = 0;
+
+    mask = clear_csr(mstatus, MSTATUS_MIE);
+
+    return mask;
+}