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921
driver/src/hw3/efuse.c
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921
driver/src/hw3/efuse.c
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/****************************************************************************
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*
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* Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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*
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* This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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* be copied by any method or incorporated into another program without
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* the express written consent of Aerospace C.Power. This Information or any portion
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* thereof remains the property of Aerospace C.Power. The Information contained herein
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* is believed to be accurate and Aerospace C.Power assumes no responsibility or
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* liability for its use in any way and conveys no license or title under
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* any patent or copyright and makes no representation or warranty that this
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* Information is free from patent or copyright infringement.
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*
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* ****************************************************************************/
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#include "os_types.h"
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#include "chip_reg_base.h"
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#include "hw_reg_api.h"
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#include "efuse_dig_reg.h"
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#include "efuse_dig_reg_s.h"
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#include "apb.h"
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#include "efuse.h"
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#include "efuse_mapping.h"
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#include "iot_errno.h"
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#include "iot_system.h"
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#include "iot_utils_api.h"
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#define EFUSE_WAIT_IDLE_TIMEOUT_CNT 10000000
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/**
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* efuse cmd
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**/
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typedef enum {
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EFUSE_CMD_PHY_BIT_PROG = 0x00,
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EFUSE_CMD_PHY_BYTE_READ,
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EFUSE_CMD_PHY_MUL_BYTE_LOAD,
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EFUSE_CMD_REG_BYTE_READ,
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EFUSE_CMD_REG_BYTE_WRITE,
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EFUSE_CMD_MAX
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} EFUSE_CMD;
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static volatile efuse_ctrl_reg_t *efuse_base = (volatile efuse_ctrl_reg_t *)EFUSE_BASEADDR;
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void efuse_init(void)
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{
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/* enable apb clock */
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apb_enable(APB_EFUSE);
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/* kl3 after power on, eFuse data will be automatically loaded into the
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* internal register, so manual loading is not required.
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*/
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}
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void efuse_deinit(void)
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{
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/* disable apb clock */
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apb_disable(APB_EFUSE);
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}
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uint8_t efuse_get_idle_statue(void)
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{
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/* idle is 1 */
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return RE_REG_FIELD(efuse_base->efuse_idle, efuse_idle);
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}
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void efuse_wait_ilde_vaild(void)
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{
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uint32_t timer_cnt = 0;
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while (!efuse_get_idle_statue()) {
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__asm volatile("nop\n");
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if (timer_cnt++ > EFUSE_WAIT_IDLE_TIMEOUT_CNT) {
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IOT_ASSERT(0);
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}
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}
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}
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void efuse_set_bit_addr(uint8_t efuse_byte_num, uint8_t bit_index)
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{
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/* efuse addr: byte for number: [15:0], bit for byte: [31:16] */
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WR_REG_FIELD(efuse_base->efuse_bit_addr, efuse_bit_addr_x, efuse_byte_num);
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WR_REG_FIELD(efuse_base->efuse_bit_addr, efuse_bit_addr_y, bit_index);
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}
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void efuse_set_read_len(uint16_t len)
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{
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efuse_base->efuse_len_read.w = (uint32_t)len;
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}
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void efuse_enable_cmd_set_mode(uint8_t mode)
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{
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IOT_ASSERT(mode < EFUSE_CMD_MAX);
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WR_REG_FIELD(efuse_base->efuse_cmd, efuse_cmd, mode);
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/* enable command vaild */
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WR_REG_FIELD(efuse_base->efuse_cmd, efuse_cmd_valid, 1);
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}
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uint16_t efuse_read_bit_ecnt(void)
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{
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return (uint16_t)efuse_base->efuse_status.w;
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}
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uint32_t efuse_read_reg(void)
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{
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return efuse_base->efuse_reg_read.w;
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}
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void efuse_write_reg(uint8_t data)
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{
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efuse_base->efuse_reg_write.w = (uint32_t)data;
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}
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uint32_t efuse_read_phy(void)
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{
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return efuse_base->efuse_phy_read.w;
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}
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uint32_t efuse_get_tpg()
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{
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return (uint32_t)RE_REG_FIELD(efuse_base->efuse_tpg, efuse_tpg);
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}
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void efuse_phy_bit_prog(uint8_t efuse_byte_num, uint8_t bit_index)
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{
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/* only opeation when efuse is in idle status */
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efuse_wait_ilde_vaild();
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efuse_set_bit_addr(efuse_byte_num, bit_index);
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efuse_enable_cmd_set_mode(EFUSE_CMD_PHY_BIT_PROG);
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efuse_wait_ilde_vaild();
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}
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uint8_t efuse_phy_byte_read(uint8_t efuse_byte_num)
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{
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/* only opeation when efuse is in idle status */
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efuse_wait_ilde_vaild();
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/* bit_index set to 0 when read the entire Byte */
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efuse_set_bit_addr(efuse_byte_num, 0);
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efuse_enable_cmd_set_mode(EFUSE_CMD_PHY_BYTE_READ);
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efuse_wait_ilde_vaild();
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return (uint8_t)efuse_read_phy();
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}
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void efuse_phy_load_to_reg(uint32_t offset, uint32_t len)
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{
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/* only opeation when efuse is in idle status */
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efuse_wait_ilde_vaild();
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/* bit_index set to 0 when read the entire Byte */
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efuse_set_bit_addr(offset, 0);
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efuse_set_read_len(len);
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efuse_enable_cmd_set_mode(EFUSE_CMD_PHY_MUL_BYTE_LOAD);
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efuse_wait_ilde_vaild();
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}
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void efuse_reg_byte_prog(uint8_t efuse_byte_num, uint8_t data)
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{
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/* only opeation when efuse is in idle status */
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efuse_wait_ilde_vaild();
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efuse_set_bit_addr(efuse_byte_num, 0);
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efuse_write_reg(data);
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efuse_enable_cmd_set_mode(EFUSE_CMD_REG_BYTE_WRITE);
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efuse_wait_ilde_vaild();
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}
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uint8_t efuse_reg_byte_read(uint8_t efuse_byte_num)
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{
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/* only opeation when efuse is in idle status */
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efuse_wait_ilde_vaild();
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/* bit_index set to 0 when read the entire Byte */
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efuse_set_bit_addr(efuse_byte_num, 0);
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efuse_enable_cmd_set_mode(EFUSE_CMD_REG_BYTE_READ);
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efuse_wait_ilde_vaild();
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return (uint8_t)efuse_read_reg();
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}
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static uint32_t efuse_read_bytes(uint32_t offset, uint8_t len, uint8_t *p)
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{
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for (uint8_t i = 0; i < len; i++) {
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p[i] = efuse_reg_byte_read(offset + i);
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}
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return 0;
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}
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uint32_t efuse_read(uint32_t offset)
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{
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/* compatible with bootram and ram program, read out 4 bytes */
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uint32_t value = 0;
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for (int i = 3; i >= 0; i--) {
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value = (value << 8) + efuse_reg_byte_read(i + offset);
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}
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return value;
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}
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uint32_t efuse_write_bytes(uint32_t offset, uint8_t len, uint8_t *val_ptr)
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{
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for (uint8_t i = 0; i < len; i++) {
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/* write in 1 bytes */
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uint8_t val = *(val_ptr + i);
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for (uint8_t j = 0; j < 8; j++) {
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if (val & (1 << j)) {
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efuse_phy_bit_prog(offset + i, j);
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}
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}
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}
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/* reload phy value to reg */
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efuse_phy_load_to_reg(offset, len);
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return 0;
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}
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uint32_t efuse_write(uint32_t offset, uint32_t val)
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{
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/* compatible with bootram and ram program, write in 4 bytes */
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uint8_t temp = 0;
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for (uint8_t i = 0; i < 4; i++) {
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temp = (uint8_t)(val >> (i * 8));
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for (uint8_t j = 0; j < 8; j++) {
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if (temp & (1 << j)) {
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efuse_phy_bit_prog(offset + i, j);
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}
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}
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}
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/* reload phy value to reg */
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efuse_phy_load_to_reg(offset, sizeof(uint32_t));
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return 0;
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}
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/* efuse data read and write function, kl3 private */
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/* only part of the API is provided for use by ATE programs */
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uint32_t efuse_get_lot_id(uint8_t *buf)
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{
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uint8_t index = CFG_EFUSE_MAPPING_ATE_SECTION_W0_ADDR;
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if (buf == NULL) {
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return ERR_FAIL;
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}
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for (uint8_t i = 0; i < 6; i++) {
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buf[i] = efuse_reg_byte_read(index + i);
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}
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return ERR_OK;
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}
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uint32_t efuse_get_wafer_id()
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{
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uint8_t index = CFG_EFUSE_MAPPING_ATE_SECTION_W1_ADDR +
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(EFUSE_FUNC_ATE_WAFER_ID_OFFSET >> 3);
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return efuse_reg_byte_read(index);
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}
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uint32_t efuse_get_die_x_coordinate()
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{
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uint8_t index = CFG_EFUSE_MAPPING_ATE_SECTION_W1_ADDR +
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(EFUSE_FUNC_ATE_DIE_X_COORDINATE_OFFSET >> 3);
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return efuse_reg_byte_read(index);
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}
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uint32_t efuse_get_die_y_coordinate()
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{
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uint8_t index = CFG_EFUSE_MAPPING_ATE_SECTION_W2_ADDR +
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(EFUSE_FUNC_ATE_DIE_Y_COORDINATE_OFFSET >> 3);
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return efuse_reg_byte_read(index);
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}
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uint32_t efuse_get_wafer_rev_record()
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{
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uint8_t index = CFG_EFUSE_MAPPING_ATE_SECTION_W2_ADDR +
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(EFUSE_FUNC_ATE_WAFER_REV_RECORD_OFFSET >> 3);
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return efuse_reg_byte_read(index);
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}
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uint32_t efuse_get_ft_pass_flag(void)
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{
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uint8_t index = CFG_EFUSE_MAPPING_ATE_SECTION_W2_ADDR +
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(EFUSE_FUNC_ATE_FT_PASS_FLAG_OFFSET >> 3);
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return (efuse_reg_byte_read(index) & 0xf);
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}
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uint32_t efuse_get_analog_bin_ver(void)
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{
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uint8_t index = CFG_EFUSE_MAPPING_ATE_SECTION_W2_ADDR +
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(EFUSE_FUNC_ATE_ANALOG_BIN_VER_OFFSET >> 3);
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return (efuse_reg_byte_read(index) >> 4);
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}
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uint8_t efuse_get_dcdc_trim(void)
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{
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uint8_t index = CFG_EFUSE_MAPPING_ATE_SECTION_W2_ADDR +
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(EFUSE_FUNC_ATE_D_VREF_TUNE_DCDC_OFFSET >> 3);
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return (efuse_reg_byte_read(index) & 0xf);
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}
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uint32_t efuse_get_flash_ldo_out_trim(void)
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{
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uint8_t index = CFG_EFUSE_MAPPING_ATE_SECTION_W2_ADDR +
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(EFUSE_FUNC_ATE_FLASH_LDO_OUT_TRIM_18_OFFSET >> 3);
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return (efuse_reg_byte_read(index) >> 4);
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}
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uint32_t efuse_set_flash_ldo_out_trim(ate_ldo_value_e ldo_value)
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{
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uint8_t ldo_value_temp;
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uint8_t index = CFG_EFUSE_MAPPING_ATE_SECTION_W2_ADDR +
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(EFUSE_FUNC_ATE_FLASH_LDO_OUT_TRIM_18_OFFSET >> 3);
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if (ldo_value >= ATE_LDO_MAX || ldo_value < 0) {
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return ERR_FAIL;
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}
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ldo_value_temp = efuse_reg_byte_read(index) | (ldo_value << 4);
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efuse_write_bytes(index, 1, &ldo_value_temp);
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return ERR_OK;
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}
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uint32_t efuse_get_d_mdll_ldo_vref_trim(void)
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{
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uint8_t index = CFG_EFUSE_MAPPING_ATE_SECTION_W3_ADDR +
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(EFUSE_FUNC_ATE_D_MDLL_LDOVREF_TRIM_OFFSET >> 3);
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return (efuse_reg_byte_read(index) & 0xf);
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}
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uint32_t efuse_get_d_bg_vbg_cntl(void)
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{
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uint8_t index = CFG_EFUSE_MAPPING_ATE_SECTION_W3_ADDR +
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(EFUSE_FUNC_ATE_D_BG_VBG_CNTL_OFFSET >> 3);
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return ((efuse_reg_byte_read(index) >> 4) & 0x7);
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}
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uint32_t efuse_get_d_bg_iccal(void)
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{
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uint8_t index = CFG_EFUSE_MAPPING_ATE_SECTION_W3_ADDR +
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(EFUSE_FUNC_ATE_D_BG_ICCAL_OFFSET >> 3);
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return (efuse_reg_byte_read(index) & 0x1f);
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}
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uint32_t efuse_get_rx_adc_vcm_ctrl(void)
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{
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uint8_t index = CFG_EFUSE_MAPPING_ATE_SECTION_W3_ADDR +
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(EFUSE_FUNC_ATE_RX_ADC_VCM_CTRL_OFFSET >> 3);
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return ((efuse_reg_byte_read(index) >> 5) & 0x7);
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}
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uint32_t efuse_get_flash_ldo_out_trim_2v5(void)
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{
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uint8_t index = CFG_EFUSE_MAPPING_ATE_SECTION_W3_ADDR +
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(EFUSE_FUNC_ATE_FLASH_LDO_OUT_TRIM_25_OFFSET >> 3);
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return (efuse_reg_byte_read(index) & 0xf);
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}
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uint16_t efuse_get_sadc_meter_dc_offset_code(void)
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{
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uint8_t byte_index;
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uint16_t value = 0;
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byte_index = CFG_EFUSE_MAPPING_SADC_SECTION_W30_ADDR +
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(EFUSE_FUNC_SADC_METER_DC_OFFSET_OFFSET >> 3);
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efuse_read_bytes(byte_index, sizeof(value), (uint8_t*)&value);
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return value;
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}
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uint16_t efuse_get_sadc_meter_dc_offset_code_n12db(void)
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{
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uint8_t byte_index;
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uint16_t value = 0;
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byte_index = CFG_EFUSE_MAPPING_SADC_2_SECTION_W26_ADDR +
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(EFUSE_FUNC_SADC_2_METER_DC_OFFSET_N12DB_OFFSET >> 3);
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efuse_read_bytes(byte_index, sizeof(value), (uint8_t*)&value);
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return value;
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}
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uint16_t efuse_get_sadc_meter_dc_offset_code_n6db(void)
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{
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uint8_t byte_index;
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uint16_t value = 0;
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byte_index = CFG_EFUSE_MAPPING_SADC_2_SECTION_W26_ADDR +
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(EFUSE_FUNC_SADC_2_METER_DC_OFFSET_N6DB_OFFSET >> 3);
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efuse_read_bytes(byte_index, sizeof(value), (uint8_t*)&value);
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return value;
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}
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uint16_t efuse_get_sadc_meter_dc_offset_code_12db(void)
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{
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uint8_t byte_index;
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uint16_t value = 0;
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byte_index = CFG_EFUSE_MAPPING_SADC_2_SECTION_W27_ADDR +
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(EFUSE_FUNC_SADC_2_METER_DC_OFFSET_12DB_OFFSET >> 3);
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efuse_read_bytes(byte_index, sizeof(value), (uint8_t*)&value);
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return value;
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}
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uint16_t efuse_get_sadc_meter_dc_offset_code_24db(void)
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{
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uint8_t byte_index;
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uint16_t value = 0;
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byte_index = CFG_EFUSE_MAPPING_SADC_2_SECTION_W27_ADDR +
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(EFUSE_FUNC_SADC_2_METER_DC_OFFSET_24DB_OFFSET >> 3);
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efuse_read_bytes(byte_index, sizeof(value), (uint8_t*)&value);
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return value;
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}
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||||
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uint16_t efuse_get_sadc_meter_vref_code(void)
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{
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uint8_t byte_index;
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uint16_t value = 0;
|
||||
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byte_index = CFG_EFUSE_MAPPING_SADC_SECTION_W31_ADDR +
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(EFUSE_FUNC_SADC_METER_VREF_OFFSET >> 3);
|
||||
efuse_read_bytes(byte_index, sizeof(value), (uint8_t*)&value);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
uint16_t efuse_get_sadc_meter_vcm_code(void)
|
||||
{
|
||||
uint8_t byte_index;
|
||||
uint16_t value = 0;
|
||||
|
||||
byte_index = CFG_EFUSE_MAPPING_SADC_SECTION_W31_ADDR +
|
||||
(EFUSE_FUNC_SADC_METER_VCM_OFFSET >> 3);
|
||||
efuse_read_bytes(byte_index, sizeof(value), (uint8_t*)&value);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
uint16_t efuse_get_sadc_tpid_dc_offset_code(void)
|
||||
{
|
||||
uint8_t byte_index;
|
||||
uint16_t value = 0;
|
||||
|
||||
byte_index = CFG_EFUSE_MAPPING_SADC_SECTION_W29_ADDR +
|
||||
(EFUSE_FUNC_SADC_TPID_DC_OFFSET_OFFSET >> 3);
|
||||
efuse_read_bytes(byte_index, sizeof(value), (uint8_t*)&value);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
uint16_t efuse_get_sadc_tpid_dc_offset_code_n12db(void)
|
||||
{
|
||||
uint8_t byte_index;
|
||||
uint16_t value = 0;
|
||||
|
||||
byte_index = CFG_EFUSE_MAPPING_SADC_2_SECTION_W24_ADDR +
|
||||
(EFUSE_FUNC_SADC_2_TPID_DC_OFFSET_N12DB_OFFSET >> 3);
|
||||
efuse_read_bytes(byte_index, sizeof(value), (uint8_t*)&value);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
uint16_t efuse_get_sadc_tpid_dc_offset_code_n6db(void)
|
||||
{
|
||||
uint8_t byte_index;
|
||||
uint16_t value = 0;
|
||||
|
||||
byte_index = CFG_EFUSE_MAPPING_SADC_2_SECTION_W24_ADDR +
|
||||
(EFUSE_FUNC_SADC_2_TPID_DC_OFFSET_N6DB_OFFSET >> 3);
|
||||
efuse_read_bytes(byte_index, sizeof(value), (uint8_t*)&value);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
uint16_t efuse_get_sadc_tpid_dc_offset_code_12db(void)
|
||||
{
|
||||
uint8_t byte_index;
|
||||
uint16_t value = 0;
|
||||
|
||||
byte_index = CFG_EFUSE_MAPPING_SADC_2_SECTION_W25_ADDR +
|
||||
(EFUSE_FUNC_SADC_2_TPID_DC_OFFSET_12DB_OFFSET >> 3);
|
||||
efuse_read_bytes(byte_index, sizeof(value), (uint8_t*)&value);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
uint16_t efuse_get_sadc_tpid_dc_offset_code_24db(void)
|
||||
{
|
||||
uint8_t byte_index;
|
||||
uint16_t value = 0;
|
||||
|
||||
byte_index = CFG_EFUSE_MAPPING_SADC_2_SECTION_W25_ADDR +
|
||||
(EFUSE_FUNC_SADC_2_TPID_DC_OFFSET_24DB_OFFSET >> 3);
|
||||
efuse_read_bytes(byte_index, sizeof(value), (uint8_t*)&value);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
uint16_t efuse_get_sadc_tpid_vref_code(void)
|
||||
{
|
||||
uint8_t byte_index;
|
||||
uint16_t value = 0;
|
||||
|
||||
byte_index = CFG_EFUSE_MAPPING_SADC_SECTION_W29_ADDR +
|
||||
(EFUSE_FUNC_SADC_TPID_VREF_OFFSET >> 3);
|
||||
efuse_read_bytes(byte_index, sizeof(value), (uint8_t*)&value);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
uint16_t efuse_get_sadc_tpid_vcm_code(void)
|
||||
{
|
||||
uint8_t byte_index;
|
||||
uint16_t value = 0;
|
||||
|
||||
byte_index = CFG_EFUSE_MAPPING_SADC_SECTION_W30_ADDR +
|
||||
(EFUSE_FUNC_SADC_TPID_VCM_OFFSET >> 3);
|
||||
efuse_read_bytes(byte_index, sizeof(value), (uint8_t*)&value);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
void efuse_get_mac_addr(uint8_t *mac)
|
||||
{
|
||||
if (mac == NULL) {
|
||||
return;
|
||||
}
|
||||
|
||||
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
||||
uint8_t index = CFG_EFUSE_MAPPING_ATE_SECTION_W4_ADDR +
|
||||
(EFUSE_FUNC_ATE_MAC_ADDR0_OFFSET >> 3);
|
||||
|
||||
/* mac addr len=6 */
|
||||
for (uint8_t i = 0; i < 6; i++) {
|
||||
mac[i] = efuse_reg_byte_read(index + i);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void efuse_set_mac_addr(uint8_t *mac)
|
||||
{
|
||||
uint32_t index = CFG_EFUSE_MAPPING_ATE_SECTION_W4_ADDR +
|
||||
(EFUSE_FUNC_ATE_MAC_ADDR0_OFFSET >> 3);
|
||||
/* mac addr len=6 */
|
||||
efuse_write_bytes(index, 6, mac);
|
||||
}
|
||||
|
||||
void efuse_set_chip_id(uint32_t chipid)
|
||||
{
|
||||
/* | chid_id[15:12] | chip_id[11:8] | chip_id[7:4] | chip_id[3:0] |
|
||||
* | project[3:0] | wafer[3:0] | mark[3:0] | sip[3:0] |
|
||||
*/
|
||||
uint32_t chipid_w = (((chipid >> 4) & 0xFF) | ((chipid & 0xF) << 8) |
|
||||
((chipid & 0xF000))) & 0xFFFF;
|
||||
uint32_t index = CFG_EFUSE_MAPPING_ATE_SECTION_W3_ADDR +
|
||||
(EFUSE_FUNC_MARK_OFFSET >> 3);
|
||||
|
||||
/* chip id: [15:12] wafer_version [11:8] mark [7:0] sip */
|
||||
efuse_write_bytes(index, 2, (uint8_t *)&chipid_w);
|
||||
}
|
||||
|
||||
uint32_t efuse_get_chip_id(void)
|
||||
{
|
||||
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
||||
uint32_t chipid = 0;
|
||||
uint8_t byte_index;
|
||||
uint8_t mark_and_wafer, sip_and_project;
|
||||
|
||||
/* | chid_id[15:12] | chip_id[11:8] | chip_id[7:4] | chip_id[3:0] |
|
||||
* | project[3:0] | wafer[3:0] | mark[3:0] | sip[3:0] |
|
||||
*/
|
||||
byte_index = CFG_EFUSE_MAPPING_ATE_SECTION_W3_ADDR +
|
||||
(EFUSE_FUNC_MARK_OFFSET >> 3);
|
||||
mark_and_wafer = efuse_reg_byte_read(byte_index);
|
||||
|
||||
byte_index = CFG_EFUSE_MAPPING_ATE_SECTION_W4_ADDR +
|
||||
(EFUSE_FUNC_SIP_OFFSET >> 3);
|
||||
sip_and_project = efuse_reg_byte_read(byte_index);
|
||||
|
||||
chipid = ((sip_and_project & 0xF0) << 8) | (mark_and_wafer << 4) |
|
||||
(sip_and_project & 0xF);
|
||||
|
||||
return chipid & 0xFFFF;
|
||||
#else
|
||||
return CHIP_ID_HZ3211_V1A;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* about efuse_set_sub_id:
|
||||
* 1.这个函数只应该被 ram.bin 调用;
|
||||
* 2.ate efuse内容检查是不检查sub id的值;
|
||||
* 3.上层应用，sub id和chip id会被使用.
|
||||
* 底层应用，sub id不牵扯任何芯片资源;
|
||||
*/
|
||||
void efuse_set_sub_id(uint32_t subid)
|
||||
{
|
||||
/* | sub_id[15:12] | sub_id[11:8] | sub_id[7:4] | sub_id[3:0] |
|
||||
* | project[3:0] | wafer[3:0] | mark[3:0] | sip[3:0] |
|
||||
*/
|
||||
uint32_t subid_w = (((subid >> 4) & 0xFF) | ((subid & 0xF) << 8) |
|
||||
((subid & 0xF000))) & 0xFFFF;
|
||||
uint32_t index = CFG_EFUSE_MAPPING_PATCH_SECTION_W28_ADDR +
|
||||
(EFUSE_FUNC_PATCH_SUB_MARK_OFFSET >> 3);
|
||||
|
||||
/* sub id: [15:12] wafer_version [11:8] mark [7:0] sip */
|
||||
efuse_write_bytes(index, 2, (uint8_t *)&subid_w);
|
||||
}
|
||||
|
||||
uint32_t efuse_get_sub_id(void)
|
||||
{
|
||||
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
||||
uint32_t subid = 0;
|
||||
uint8_t byte_index;
|
||||
uint8_t mark_and_wafer, sip_and_project;
|
||||
|
||||
/* | sub_id[15:12] | sub_id[11:8] | sub_id[7:4] | sub_id[3:0] |
|
||||
* | project[3:0] | wafer[3:0] | mark[3:0] | sip[3:0] |
|
||||
*/
|
||||
byte_index = CFG_EFUSE_MAPPING_PATCH_SECTION_W28_ADDR +
|
||||
(EFUSE_FUNC_PATCH_SUB_MARK_OFFSET >> 3);
|
||||
mark_and_wafer = efuse_reg_byte_read(byte_index);
|
||||
|
||||
byte_index = CFG_EFUSE_MAPPING_PATCH_SECTION_W28_ADDR +
|
||||
(EFUSE_FUNC_PATCH_SUB_SIP_OFFSET >> 3);
|
||||
sip_and_project = efuse_reg_byte_read(byte_index);
|
||||
|
||||
subid = ((sip_and_project & 0xF0) << 8) | (mark_and_wafer << 4) |
|
||||
(sip_and_project & 0xF);
|
||||
|
||||
return subid & 0xFFFF;
|
||||
#else
|
||||
return CHIP_ID_HZ3211_V1A;
|
||||
#endif
|
||||
}
|
||||
|
||||
void efuse_get_sadc_calib_code(uint8_t id, float *vref,
|
||||
float *vcm, float *dc_offset, uint8_t dc_offset_array_len)
|
||||
{
|
||||
if (dc_offset_array_len < 5) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (id == 0) { //meter
|
||||
if (dc_offset) {
|
||||
/* the order is the same as sadc_hw_calib_gain_t */
|
||||
dc_offset[0] = (float)efuse_get_sadc_meter_dc_offset_code_n12db();
|
||||
dc_offset[1] = (float)efuse_get_sadc_meter_dc_offset_code_n6db();
|
||||
dc_offset[2] = (float)efuse_get_sadc_meter_dc_offset_code();
|
||||
dc_offset[3] = (float)efuse_get_sadc_meter_dc_offset_code_12db();
|
||||
dc_offset[4] = (float)efuse_get_sadc_meter_dc_offset_code_24db();
|
||||
}
|
||||
if (vref) {
|
||||
*vref = (float)efuse_get_sadc_meter_vref_code();
|
||||
}
|
||||
if (vcm) {
|
||||
*vcm = (float)efuse_get_sadc_meter_vcm_code();
|
||||
}
|
||||
} else if (id == 1) { //tpid
|
||||
if (dc_offset) {
|
||||
/* the order is the same as sadc_hw_calib_gain_t */
|
||||
dc_offset[0] = (float)efuse_get_sadc_tpid_dc_offset_code_n12db();
|
||||
dc_offset[1] = (float)efuse_get_sadc_tpid_dc_offset_code_n6db();
|
||||
dc_offset[2] = (float)efuse_get_sadc_tpid_dc_offset_code();
|
||||
dc_offset[3] = (float)efuse_get_sadc_tpid_dc_offset_code_12db();
|
||||
dc_offset[4] = (float)efuse_get_sadc_tpid_dc_offset_code_24db();
|
||||
}
|
||||
if (vref) {
|
||||
*vref = (float)efuse_get_sadc_tpid_vref_code();
|
||||
}
|
||||
if (vcm) {
|
||||
*vcm = (float)efuse_get_sadc_tpid_vcm_code();
|
||||
}
|
||||
} else {
|
||||
/* do nothing */
|
||||
}
|
||||
|
||||
/* efuse saves the sampling values that retain 2 decimal place */
|
||||
*vref /= EFUSE_SADC_SAMPLING_CODE_MULTIPLE;
|
||||
*vcm /= EFUSE_SADC_SAMPLING_CODE_MULTIPLE;
|
||||
for (uint8_t i = 0; i < 5; i++) {
|
||||
dc_offset[i] /= EFUSE_SADC_SAMPLING_CODE_MULTIPLE;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t efuse_get_rf_tx_iqm_dc_calib_info(uint8_t *i_mag, uint8_t *q_mag,
|
||||
uint8_t *i_phase, uint8_t *q_phase, int8_t *i_dc, int8_t *q_dc)
|
||||
{
|
||||
|
||||
efuse_section_ana_t ana = {0};
|
||||
uint32_t index = CFG_EFUSE_MAPPING_SYS_ANA_SECTION_W10_ADDR +
|
||||
(EFUSE_FUNC_ANA_DATA0_OFFSET >> 3);
|
||||
efuse_read_bytes(index, sizeof(ana), (uint8_t *)&ana);
|
||||
if (ana.valid_mark & EFULSE_SEC_ANA_VALID_MARK_RF_TX_IQM_DC_CALIB) {
|
||||
*i_mag = ana.tx_iqm_dc.i_mag;
|
||||
*q_mag = ana.tx_iqm_dc.q_mag;
|
||||
*i_phase = ana.tx_iqm_dc.i_phase;
|
||||
*q_phase = ana.tx_iqm_dc.q_phase;
|
||||
*i_dc = ana.tx_iqm_dc.i_dc;
|
||||
*q_dc = ana.tx_iqm_dc.i_dc;
|
||||
return ERR_OK;
|
||||
}
|
||||
return ERR_NOT_EXIST;
|
||||
}
|
||||
|
||||
/*******BOND FUNCTION BEGIN********/
|
||||
|
||||
uint32_t efuse_set_bond_data(uint32_t bond_data)
|
||||
{
|
||||
uint32_t byte_index;
|
||||
uint32_t bond_data_tmp;
|
||||
|
||||
bond_data_tmp = (efuse_read(CFG_EFUSE_MAPPING_BOND_SECTION_W6_ADDR) &
|
||||
efuse_read(CFG_EFUSE_MAPPING_BOND_SECTION_W7_ADDR)) |
|
||||
bond_data;
|
||||
byte_index = CFG_EFUSE_MAPPING_BOND_SECTION_W6_ADDR;
|
||||
efuse_write(byte_index, bond_data_tmp);
|
||||
byte_index = CFG_EFUSE_MAPPING_BOND_SECTION_W7_ADDR;
|
||||
efuse_write(byte_index, bond_data_tmp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t efuse_get_bond_data(bond_type type)
|
||||
{
|
||||
uint32_t ret_data;
|
||||
uint32_t bond_data, bond_data_backup;
|
||||
|
||||
switch (type) {
|
||||
case BOND_CONFIG:
|
||||
bond_data = efuse_read(CFG_EFUSE_MAPPING_BOND_SECTION_W6_ADDR);
|
||||
ret_data = bond_data;
|
||||
break;
|
||||
case BOND_BACKUP:
|
||||
bond_data_backup = efuse_read(CFG_EFUSE_MAPPING_BOND_SECTION_W7_ADDR);
|
||||
ret_data = bond_data_backup;
|
||||
break;
|
||||
case BOND_DATA:
|
||||
default:
|
||||
bond_data = efuse_read(CFG_EFUSE_MAPPING_BOND_SECTION_W6_ADDR);
|
||||
bond_data_backup = efuse_read(CFG_EFUSE_MAPPING_BOND_SECTION_W7_ADDR);
|
||||
ret_data = bond_data & bond_data_backup;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret_data;
|
||||
}
|
||||
|
||||
/*******BOND FUNCTION END********/
|
||||
|
||||
/* efuse data read and write function, kl public */
|
||||
uint8_t efuse_check_data()
|
||||
{
|
||||
/* 0x00: check succeed; other: the corresponding item fails to be verified.
|
||||
* bit 0: chip id check result;
|
||||
* bit 1: mac address check result;
|
||||
* bit 2: ate calibration check result;
|
||||
* bit 3: sadc meter check result.
|
||||
* bit 4: sadc tpid check result.
|
||||
*/
|
||||
uint8_t ret_st = 0x00;
|
||||
|
||||
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
||||
uint32_t ate_info, chipid, ate_ver;
|
||||
uint8_t mac_info[IOT_MAC_ADDR_LEN] = {0};
|
||||
uint8_t i = 0;
|
||||
|
||||
/* check chip id */
|
||||
chipid = efuse_get_chip_id();
|
||||
if (chipid == 0) {
|
||||
ret_st |= 1 << 0;
|
||||
}
|
||||
|
||||
/* check mac */
|
||||
efuse_get_mac_addr(mac_info);
|
||||
for (i = 0; i < IOT_MAC_ADDR_LEN; i++) {
|
||||
if (mac_info[i] != 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (i >= IOT_MAC_ADDR_LEN) {
|
||||
ret_st |= 1 << 1;
|
||||
}
|
||||
|
||||
ate_ver = efuse_get_analog_bin_ver();
|
||||
/* check ate */
|
||||
ate_info = ate_ver;
|
||||
ate_info |= efuse_get_ft_pass_flag();
|
||||
ate_info |= efuse_get_dcdc_trim();
|
||||
ate_info |= efuse_get_flash_ldo_out_trim();
|
||||
ate_info |= efuse_get_d_mdll_ldo_vref_trim();
|
||||
ate_info |= efuse_get_d_bg_vbg_cntl();
|
||||
ate_info |= efuse_get_d_bg_iccal();
|
||||
ate_info |= efuse_get_rx_adc_vcm_ctrl();
|
||||
ate_info |= efuse_get_flash_ldo_out_trim_2v5();
|
||||
if (ate_info == 0) {
|
||||
ret_st |= 1 << 2;
|
||||
}
|
||||
|
||||
/* check sadc meter */
|
||||
ate_info = efuse_get_sadc_meter_dc_offset_code();
|
||||
ate_info |= efuse_get_sadc_meter_vref_code();
|
||||
ate_info |= efuse_get_sadc_meter_vcm_code();
|
||||
if (ate_ver >= EFUSE_ATE_BIN_VERSION_V2) {
|
||||
ate_info |= efuse_get_sadc_meter_dc_offset_code_n12db();
|
||||
ate_info |= efuse_get_sadc_meter_dc_offset_code_n6db();
|
||||
ate_info |= efuse_get_sadc_meter_dc_offset_code_12db();
|
||||
ate_info |= efuse_get_sadc_meter_dc_offset_code_24db();
|
||||
}
|
||||
if (ate_info == 0) {
|
||||
ret_st |= 1 << 3;
|
||||
}
|
||||
|
||||
/* check sadc tpid */
|
||||
if (ate_ver >= EFUSE_ATE_BIN_VERSION_V2) {
|
||||
ate_info = efuse_get_sadc_tpid_dc_offset_code();
|
||||
ate_info |= efuse_get_sadc_tpid_vref_code();
|
||||
ate_info |= efuse_get_sadc_tpid_vcm_code();
|
||||
ate_info |= efuse_get_sadc_tpid_dc_offset_code_n12db();
|
||||
ate_info |= efuse_get_sadc_tpid_dc_offset_code_n6db();
|
||||
ate_info |= efuse_get_sadc_tpid_dc_offset_code_12db();
|
||||
ate_info |= efuse_get_sadc_tpid_dc_offset_code_24db();
|
||||
if (ate_info == 0) {
|
||||
ret_st |= (1 << 4);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret_st;
|
||||
}
|
||||
|
||||
bool_t efuse_prog_done_check()
|
||||
{
|
||||
if (efuse_get_idle_statue()) {
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
void efuse_write_prog_done()
|
||||
{
|
||||
efuse_wait_ilde_vaild();
|
||||
}
|
||||
|
||||
uint32_t efuse_protect()
|
||||
{
|
||||
/* not support */
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t efuse_protect_off()
|
||||
{
|
||||
/* not support */
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t efuse_get_wafer_version()
|
||||
{
|
||||
/* not support */
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t efuse_get_reserve_version()
|
||||
{
|
||||
/* not support */
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t efuse_get_package_version()
|
||||
{
|
||||
/* not support */
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint8_t efuse_get_pmu_ldo_trim()
|
||||
{
|
||||
/* not support */
|
||||
return 0;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user