andy/kunlun
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

初始提交

Browse Source
This commit is contained in:
andy
2024-09-28 14:24:04 +08:00
commit c756587541
5564 changed files with 2413077 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

63
dtest/dtest3/kl3_rom_patch_test/Makefile Normal file
View File

@@ -0,0 +1,63 @@
# OUTPUT type
# 1 - .out
# 2 - .a
# 3 - .so
OUTPUT_TYPE = 1
OUTPUT_NAME = kl3_rom_patch
SUB_DIRS = $(TOPDIR)/dtest/dtest3/common $(TOPDIR)/os
# .h files dir
ADD_INCLUDE += $(TOPDIR)/plc/halphy/inc $(TOPDIR)/inc/compiler/gcc $(TOPDIR)/inc $(TOPDIR)/inc/io_lib $(TOPDIR)/inc/driver $(TOPDIR)/inc/uart $(TOPDIR)/inc/plc_lib $(TOPDIR)/inc/ipc $(TOPDIR)/inc/os_shim $(TOPDIR)/inc/pkt $(TOPDIR)/inc/utils $(TOPDIR)/plc/inc $(TOPDIR)/inc/cli $(TOPDIR)/cli/communicator $(TOPDIR)/inc/dbglog $(TOPDIR)/inc/ftm $(TOPDIR)/plc/halmac/inc $(TOPDIR)/plc/halmac/hw/inc/desc $(TOPDIR)/driver/inc $(TOPDIR)/driver/inc/pib
PRE_MARCO += _MODULE_NAME_=\"ROM_PATCH\"
PRE_MARCO += _MODULE_VERSION_=\"V1.0.0\"
LD_SCRIPT = rom_patch_link_soc.lds
OPT_FLAG = -O0 -g
ifeq ($(gcc), arm)
ADD_INCLUDE += $(TOPDIR)/os/freertos/src/portable/ARM_CM3
else
ADD_INCLUDE += $(TOPDIR)/os/freertos/src/portable/RISCV $(TOPDIR)/dtest/dtest3/common
endif
ifeq ($(gcc),arm)
ADD_LIB = cm3
ADD_LIBDIR = $(TOPDIR)/startup/cm3
else
ifeq ($(target), kunlun3)
ADD_LIB = riscv
ADD_LIBDIR =$(TOPDIR)/startup/riscv3
ADD_INCLUDE += $(TOPDIR)/driver/src/hw3/inc
endif
endif
# lib dir
ADD_LIBDIR += $(TOPDIR)/driver $(TOPDIR)/common $(TOPDIR)/os #$(TOPDIR)/pib $(TOPDIR)/plc
# lib need to ld together
ADD_LIB += driver common os
#####################################################
ifdef TOPDIR
include $(TOPDIR)/build/makefile.cfg
else
include $(CURDIR)/build/makefile.cfg
TOPDIR = $(CURDIR)
export TOPDIR
endif
dump:
$(OBJDUMP) -D -S -l $(OUTPUT_FULL_NAME) > $(OUTPUT_FULL_NAME).dump
# display the obj files and output name
debug:
@echo TOPDIR=$(TOPDIR)
@echo OUTPUT_LIB=$(OUTPUT_FULL_NAME)
@echo DEPS=$(DEPS)
@echo OBJECTS=$(OBJECTS)
@echo SRCS=$(SRCS)
@echo OBJECTS folder=$(foreach dirname, $(SUB_DIRS), $(addprefix $(BIN_DIR)/, $(dirname)))
@echo output_name=$(OUTPUT_FULL_NAME)

1335
dtest/dtest3/kl3_rom_patch_test/encoding.h Normal file
View File

File diff suppressed because it is too large Load Diff

47
dtest/dtest3/kl3_rom_patch_test/func.S Normal file
View File

@@ -0,0 +1,47 @@
// See LICENSE for license details.
#include "encoding.h"
.section .func1
.globl _func1
//addr 4字节对齐 4字节指令
_func1:
lui a0,0x42
ret
.section .func2
.globl _func2
//addr 4字节对齐指令2字节长
_func2:
li a0, 15
nop
ret
.section .func3
.type _func3,@function
.globl _func3
//addr 2字节对齐 4字节指令
_func3:
/*
addi sp,sp,-32
sw s0,28(sp)
addi s0,sp,32
sw a0,-20(s0)
li a5,3
mv a0,a5
lw s0,28(sp)
addi sp,sp,32
// ret
*/
lui a0,0x43
//nop
ret
.section .func4
.globl _func4
//addr 2字节对齐指令2字节长
_func4:
li a0, 16
ret

784
dtest/dtest3/kl3_rom_patch_test/kl3_rom_patch.c Normal file
View File

@@ -0,0 +1,784 @@
/****************************************************************************
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.
****************************************************************************/
#include "hw_reg_api.h"
#include "chip_reg_base.h"
#include "apb_cache_reg.h"
#include "sram.h"
#include "smc.h"
#include "ahb.h"
#include "gp_timer.h"
#include "uart.h"
#include "dbg_io.h"
#include "iot_io_api.h"
#include "os_mem_api.h"
#include "iot_errno_api.h"
#include "dtest_printf.h"
#include "string.h"
#include "os_types.h"
#include "os_task.h"
#include "os_utils.h"
/* common includes */
#include "iot_io.h"
#include "iot_bitops.h"
#include "iot_pkt.h"
#include "iot_dbglog_api.h"
#include "iot_config.h"
/* driver includes */
#include "iot_clock.h"
#include "iot_uart.h"
#include "uart.h"
#include "apb_dma.h"
#include "dma_hw.h"
/* cli includes */
#include "iot_cli.h"
#include "iot_uart_h.h"
/* debug includes*/
#include "dbg_io.h"
/* driver includes */
#include "cpu.h"
#include "iot_gpio_api.h"
#include "hw_reg_api.h"
#include "pin_rf.h"
#include "dtest_printf.h"
#include "iot_share_task.h"
#include "wdg_reg.h"
#include "irq.h"
#include "iot_string_api.h"
#include "gpio.h"
#include "gpio_mtx.h"
#include "iot_gpio.h"
#include "iot_irq.h"
#if 1
/* os shim includes */
#include "os_types.h"
#include "os_task.h"
#include "os_utils.h"
/* common includes */
#include "iot_io.h"
#include "iot_bitops.h"
#include "iot_pkt.h"
#include "iot_ipc.h"
#include "iot_dbglog_api.h"
#include "iot_config.h"
/* driver includes */
#include "iot_clock.h"
#include "iot_uart.h"
#include "uart.h"
#include "apb_dma.h"
#include "dma_hw.h"
/* cli includes */
#include "iot_cli.h"
#include "iot_uart_h.h"
/* debug includes*/
#include "dbg_io.h"
/* driver includes */
#include "cpu.h"
#include "iot_gpio_api.h"
#include "hw_reg_api.h"
#include "pin_rf.h"
#include "dtest_printf.h"
#include "iot_share_task.h"
#include "ahb.h"
#include "rtc.h"
#include "rom_patch_hw.h"
extern int platform_init();
os_task_h test_init_handle;
static const iot_pkt_config_t test_pkt_config =
{
{
{
256,
1,
PKT_OWNER_ALL,
},
{
600,
1,
PKT_OWNER_ALL,
},
{
1100,
1,
PKT_OWNER_ALL,
},
{
2200,
1,
PKT_OWNER_ALL,
},
{
0,
0,
PKT_OWNER_NONE,
},
{
0,
0,
PKT_OWNER_NONE,
},
{
0,
0,
PKT_OWNER_NONE,
},
{
0,
0,
PKT_OWNER_NONE,
},
}
};
#define GPIO_FUNC_MASK 0x70
#define TEST_INT 64
extern void ahb_rom_patch_unlock(void);
extern void ahb_rom_patch_lock(void);
extern int ahb_rom_pathc_config(ROM_PATCH_CH ch, uint32_t index);
// BUILT V3.2.1.1, 20211206-175010
#define rom_main_itoa_fun_addr 0x000200ac //地址2字节对齐，指令2字节长
#define rom_timer_delay_us_fun_addr 0x000205f8 //地址4字节对齐，指令2字节长
#define rom_getcrc32_fun_addr 0x00020c72 //地址2字节对齐，指令4字节长
#define rom_timer_get_val_fun_addr 0x000205f0 //地址4字节对齐，指令4字节长
static volatile int flag = 0;
static volatile uint32_t loop = 0;
void my_getcrc32(void)
{
flag = 0xabcddcba;
iot_printf("my_getcrc32\r\n");
}
void my_timer_delay_us(void)
{
flag = 0xabcddcba;
iot_printf("my_timer_delay_us\r\n");
}
void my_itoa(char *p, uint32_t value)
{
iot_strcpy(p, "2222**2222");
flag = 0xabcddcba;
}
uint32_t my_timer_get_val(void)
{
flag = 0xabcddcba;
return loop;
}
typedef unsigned int(*rom_main_itoa_fun_type)(char *p, uint32_t value);
typedef void(*rom_timer_delay_us_fun_type)(uint32_t delay_us);
typedef int(*rom_getcrc32_fun_type)(uint8_t *buffer, uint32_t len);
typedef uint32_t(*rom_timer_get_val_fun_type)(void);
#define fun_ptr_def(name) \
name##_fun_type name##_ptr = (name##_fun_type) name##_fun_addr;
extern struct uart_ctrl uart_e_ctrl;
int int_mode = GPIO_INT_EDGE_RAISING;
static void gpio_func_set(uint8_t gpio_no, uint8_t func)
{
uint32_t tmp;
uint32_t addr;
addr = CFG_GPIO00_PIN_CFG_ADDR + (gpio_no << 2);
tmp = DIG_PIN_READ_REG(addr);
/* Set function */
tmp &= ~(GPIO_FUNC_MASK);
tmp |= (func<<4)&GPIO_FUNC_MASK;
/* Set pull-up */
tmp &= ~0x40;
tmp |= 0x80;
DIG_PIN_WRITE_REG(addr, tmp);
return ;
}
void gpio_task_hander(int pin)
{
dprintf("GPIO%02d has been triggered!, tri_mode:%d\n", pin, int_mode);
//os_delay(500);
iot_gpio_interrupt_enable(pin, 1);
}
void test_task_rom_patch(){
int v=0, r;
(void)v;
dprintf("test_task....\n");
gpio_func_set(TEST_INT, 0);
r = iot_gpio_open_as_interrupt(TEST_INT);
dprintf("\ngpio int open ret = %d\n", r);
r = iot_gpio_interrupt_config
(TEST_INT, int_mode, (iot_gpio_isr_func)gpio_task_hander, TEST_INT, 1);
dprintf("\ngpio int config ret = %d\n", r);
r = iot_gpio_interrupt_enable(TEST_INT, 1);
dprintf("\ngpio int config ret = %d\n", r);
/*rom patch */
#if IOT_ROM_PATCH_ENABLE
if(1) {
ahb_rom_patch_unlock();
ahb_rom_patch_clear(ROM_PATCH_CH_0);
ahb_rom_patch_clear(ROM_PATCH_CH_1);
ahb_rom_patch_clear(ROM_PATCH_CH_2);
ahb_rom_patch_clear(ROM_PATCH_CH_3);
ahb_rom_patch_config(ROM_PATCH_CH_0, rom_main_itoa_fun_addr, (uint32_t)my_itoa);//ok
ahb_rom_patch_config(ROM_PATCH_CH_1, rom_timer_delay_us_fun_addr, (uint32_t)my_timer_delay_us);//ok
ahb_rom_patch_config(ROM_PATCH_CH_2, rom_getcrc32_fun_addr, (uint32_t)my_getcrc32);//ok
ahb_rom_patch_config(ROM_PATCH_CH_3, rom_timer_get_val_fun_addr, (uint32_t)my_timer_get_val);//ok
}
fun_ptr_def(rom_main_itoa)
fun_ptr_def(rom_timer_delay_us)
fun_ptr_def(rom_getcrc32)
fun_ptr_def(rom_timer_get_val)
uint32_t t = 0;
char c = '0';
uint8_t table[]={1,2,3,4,5,6,7,8,9,10};
for(;;) {
iot_printf("\r\n*****\'%c\'==0x%02x****\r\n", c, c);
switch(c) {
case '0': {
if (1) {
t = 99;
rom_main_itoa_ptr((char *)table, t);
iot_printf("line:%d, table = %s\r\n", __LINE__, table);
c = '1';
}
break;
}
case '1' :{
rom_timer_delay_us_ptr(100);
iot_printf("line:%d\r\n", __LINE__);
c = '2';
break;
}
case '2' : {
t = rom_getcrc32_ptr(table, sizeof(table)/sizeof(table[0]));
iot_printf("line:%d\r\n", __LINE__);
c = '3';
break;
}
case '3' : {
t = rom_timer_get_val_ptr();
iot_printf("line:%d, t=%d, loop=%d\r\n", __LINE__, t, loop ++);
c = '0';
break;
}
default : {
c = '0';
flag = 0xabcddcba;
}
}
while(flag != 0xabcddcba)
{
iot_printf("wait\r\n");
os_delay(1000);
}
flag = 0;
iot_printf("endloop .\r\n");
os_delay(1000);
}
#else /*#if IOT_ROM_PATCH_ENABLE*/
for(;;) {
os_delay(1000);
iot_printf("Please enable macro IOT_ROM_PATCH_ENABLE for test rom patch\r\n");
}
#endif /*#if IOT_ROM_PATCH_ENABLE*/
}
void test_init()
{
/* init common modules */
iot_bitops_init();
/* init os related modules and utilities */
os_utils_init();
/* init dbglog module */
iot_dbglog_init();
/* init pkt module */
iot_pkt_init(&test_pkt_config);
/* init ipc module */
//iot_ipc_init();
/*init uart module*/
iot_uart_init(1);
iot_share_task_init();
/* init gpio module */
iot_gpio_module_init();
test_task_rom_patch();
}
void iot_task_1(void *arg)
{
dprintf("task 1 entry....\n");
test_init();
for(;;) {
os_delete_task(test_init_handle);
dprintf("task 1 running....\n");
os_delay(1000);
}
}
int32_t iot_task_init()
{
/* start plc lib task */
test_init_handle = os_create_task(iot_task_1, NULL, 9);
//create the tasks;
if(test_init_handle != NULL) {
dprintf("task 1 init successfully...\n");
}
return 0;
}
int32_t iot_task_start()
{
//start the tasks;
os_start_kernel();
return 0;
}
static void cache_init()
{
cache_enable(AHB_CACHE_D0);
cache_set_buffer_mode(AHB_CACHE_D0, 1);
cache_enable(AHB_CACHE_D1);
cache_set_buffer_mode(AHB_CACHE_D1, 1);
}
static int32_t iot_platform_init()
{
cache_init();
/*platform intialization*/
platform_init();
//resource initializations;
system_clock_init();
system_uart_init();
dbg_uart_init();
dbg_uart_stage1_init();
/* rtc init, idle used rtc lock */
iot_rtc_init();
return 0;
}
int32_t iot_module_init(void)
{
//platform intialization;
iot_platform_init();
//create all the tasks;
iot_task_init();
dprintf("starting...\n");
return 0;
}
int32_t iot_module_start(void)
{
int32_t res = 0;
res = iot_task_start();
return res;
}
#include "apb_dma.h"
int main(void)
{
//module init;
iot_module_init();
iot_module_start();
return 0;
}
#else
void test_rom_wdg_init(void);
extern void ahb_rom_patch_unlock(void);
extern void ahb_rom_patch_lock(void);
extern int ahb_rom_pathc_config(ROM_PATCH_CH ch, uint32_t index);
// BUILT V3.2.1.1, 20211206-175010
#define rom_main_itoa_fun_addr 0x000200ac //地址2字节对齐，指令2字节长 ok
#define rom_timer_delay_us_fun_addr 0x000205f8 //地址4字节对齐，指令2字节长
#define rom_getcrc32_fun_addr 0x00020c72 //地址2字节对齐，指令4字节长
#define rom_timer_get_val_fun_addr 0x000205f0 //地址4字节对齐，指令4字节长
//void rom_main_itoa(char *p, uint32_t value)
//void rom_timer_delay_us(uint32_t delay_us)
//uint32_t rom_getcrc32(uint8_t *buffer, uint32_t len)
//uint32_t rom_timer_get_val(void)
#define FUNC1_ATTR __attribute__((section(".func1")))
#define FUNC2_ATTR __attribute__((section(".func2")))
#define FUNC3_ATTR __attribute__((section(".func3")))
#define FUNC4_ATTR __attribute__((section(".func4")))
#define CORE0_TEST_PIN 64
#define _NEXTLINE_ "\r\n"
extern iot_gpio_op_t hw_gpio_api_table;
static volatile int flag = 0;
void patch_handle2(void)
{
flag = 0xabcddcba;
iot_printf("patch_handle2\r\n");
}
void patch_handle4(void)
{
flag = 0xabcddcba;
iot_printf("patch_handle4\r\n");
}
void my_itoa(char *p, uint32_t value)
{
iot_strcpy(p, "2222**2222");
flag = 0xabcddcba;
}
typedef unsigned int(*rom_main_itoa_fun_type)(char *p, uint32_t value);
typedef void(*rom_timer_delay_us_fun_type)(uint32_t delay_us);
typedef int(*rom_getcrc32_fun_type)(uint8_t *buffer, uint32_t len);
typedef uint32_t(*rom_timer_get_val_fun_type)(void);
#define fun_ptr_def(name) \
name##_fun_type name##_ptr = (name##_fun_type) name##_fun_addr;
extern struct uart_ctrl uart_e_ctrl;
char c = 0;
uint32_t IRAM_ATTR gpio_int_handler0(uint32_t vector, iot_addrword_t data)
{
if (hw_gpio_api_table.get_interrupt_status(CORE0_TEST_PIN)) {
iot_printf("Core0 irq enter...."_NEXTLINE_);
hw_gpio_api_table.clear_interrupt_status(CORE0_TEST_PIN);
}
return 0;
}
int main(void) {
//volatile uint32_t *p_reg_index, *p_reg_content;
uint32_t loop = 0;
test_rom_wdg_init();
dbg_uart_init();
iot_printf("start\r\n");
#if 0
while(1) {
volatile int i = 0;
if (uart_e_ctrl.rx_fifo_cnt(UART_PT0) > 0) {
c = (char)uart_e_ctrl.getc(UART_PT0);
iot_printf("\r\n*****%c****\r\n", c);
if ( ('0' == c) || ('1' == c) || ('2' == c) || ('3' == c)) {
iot_printf("go\r\n");
break;
}
}
i ++;
if (i >= 10000000) {
iot_printf("input 0 or 1 or 2 or 3\r\n");
}
}
#else
c = '0';
#endif
/*interrupt*/
hw_gpio_api_table.gpio_init();
gpio_pin_select(CORE0_TEST_PIN,0);
/* attach irq */
iot_irq_t gpio_irq_h = iot_interrupt_create(HAL_VECTOR_GPIO, HAL_INTR_PRI_6, CORE0_TEST_PIN, gpio_int_handler0);
iot_interrupt_attach(gpio_irq_h);
iot_interrupt_unmask(gpio_irq_h);
hw_gpio_api_table.set_gpio_mode(CORE0_TEST_PIN,GPIO_INTERRUPT);
hw_gpio_api_table.set_interrupt_mode(CORE0_TEST_PIN,GPIO_INT_EDGE_FALLING);
//
if(0) {
ahb_rom_patch_unlock();
ahb_rom_patch_clear(ROM_PATCH_CH_0);
ahb_rom_patch_clear(ROM_PATCH_CH_1);
ahb_rom_patch_clear(ROM_PATCH_CH_2);
ahb_rom_patch_clear(ROM_PATCH_CH_3);
ahb_rom_patch_config(ROM_PATCH_CH_0, rom_main_itoa_fun_addr, (uint32_t)my_itoa);
ahb_rom_patch_config(ROM_PATCH_CH_1, rom_timer_delay_us_fun_addr, (uint32_t)patch_handle4);//ok
ahb_rom_patch_config(ROM_PATCH_CH_2, rom_getcrc32_fun_addr, (uint32_t)patch_handle2);//ok
ahb_rom_patch_config(ROM_PATCH_CH_3, rom_timer_get_val_fun_addr, (uint32_t)patch_handle4);
}
fun_ptr_def(rom_main_itoa)
fun_ptr_def(rom_timer_delay_us)
fun_ptr_def(rom_getcrc32)
fun_ptr_def(rom_timer_get_val)
iot_printf("\r\nstart:\r\n");
uint32_t t = 0;
iot_printf("All func can be called\r\n");
(void)t;
while(1) {
uint8_t table[]={1,2,3,4,5,6,7,8,9,10};
iot_printf("\r\n*****\'%c\'==0x%02x****\r\n", c, c);
switch(c) {
case '0': {
if (0) {
t = 99;
rom_main_itoa_ptr((char *)table, t);
iot_printf("line:%d, table = %s\r\n", __LINE__, table);
c = '1';
}
break;
}
case '1' :{
rom_timer_delay_us_ptr(100);
iot_printf("line:%d\r\n", __LINE__);
c = '2';
break;
}
case '2' : {
t = rom_getcrc32_ptr(table, sizeof(table)/sizeof(table[0]));
iot_printf("line:%d\r\n", __LINE__);
c = '3';
break;
}
case '3' : {
t = rom_timer_get_val_ptr();
iot_printf("line:%d\r\n", __LINE__);
c = '0';
break;
}
default : {
c = '0';
}
}
iot_printf("t=%d,0x%x,c=%c\r\n", t, t, c);
while(flag != 0xabcddcba)
{
iot_printf("wait\r\n");
for(volatile int i = 0; i < 1000000; i++)
{
}
}
flag = 0;
for(volatile int i = 0; i < 1000000; i++)
{
}
iot_printf("endloop %d.\r\n", loop++);
}
iot_printf("%d\r\n", __LINE__);
while(1);
return 0;
}
void print_mem(void *addr, int bytes)
{
uint8_t *p_addr = (uint8_t *) addr;
for (int i = 0; i < bytes; i++) {
if (i % 8 == 0) {
iot_printf("\r\n");
}
iot_printf("%02x ", (*p_addr ++) & 0xff);
}
iot_printf("\r\n");
}
static void test_rom_wdg_write_reg(uint32_t wdg_num, uint32_t addr, uint32_t value)
{
if (0 == wdg_num) {
WDG0_WRITE_REG(CFG_WDG_PROTECT_REG_ADDR, 0x57444750);
WDG0_WRITE_REG(addr, value);
} else if (0 == wdg_num) {
WDG1_WRITE_REG(CFG_WDG_PROTECT_REG_ADDR, 0x57444750);
WDG1_WRITE_REG(addr, value);
} else if (0 == wdg_num) {
WDG2_WRITE_REG(CFG_WDG_PROTECT_REG_ADDR, 0x57444750);
WDG2_WRITE_REG(addr, value);
}
return;
}
void test_rom_wdg_set (uint32_t wdg, uint32_t ena)
{
uint32_t data, ena_bit;
/* Enable apb clock. */
//rom_apb_wdg_enable(wdg);
flag = 0xabcddcba;
iot_printf("\r\n%s\r\n", __func__);
return ;
ena_bit = ena ? 1 : 0;
/* Enable the clock even if this wdg will be shutdown. */
//apb_enable(apb_bit);
/* Set compare cycle, 20 seconds timeout. */
test_rom_wdg_write_reg(wdg, CFG_WDG_CMP_ADDR, 3200);
if (ena_bit) {
/* Set feed/cpurst/fullrst timeout time same as compare-timeout time. */
data = 0;
REG_FIELD_SET(WDG_TIMEOUT_CMP, data, 100);
REG_FIELD_SET(WDG_CPURST_CMP, data, 100);
REG_FIELD_SET(WDG_FULLRST_CMP, data, 100);
test_rom_wdg_write_reg(wdg, CFG_WDG_INT_RST_CMP_ADDR, data);
}
/* Just enable full-reset counter. */
data = 0;
REG_FIELD_SET(WDG_FULLRST_CNT_EN, data, ena_bit);
REG_FIELD_SET(WDG_CNT_EN, data, ena_bit);
test_rom_wdg_write_reg(wdg, CFG_WDG_CTL0_ADDR, data);
/* Just enable full-reset interrupt. */
data = 0;
REG_FIELD_SET(WDG_FULLRST_EN, data, ena_bit);
REG_FIELD_SET(WDG_INTER_EN, data, ena_bit);
test_rom_wdg_write_reg(wdg, CFG_WDG_CTL1_ADDR, data);
return;
}
void test_rom_wdg_init(void)
{
/* Just enable WDG0. */
test_rom_wdg_set(0, 0);
test_rom_wdg_set(1, 0);
test_rom_wdg_set(2, 0);
return;
}
#endif

228
dtest/dtest3/kl3_rom_patch_test/rom_patch_link_soc.lds Executable file
View File

@@ -0,0 +1,228 @@
OUTPUT_ARCH( "riscv" )
ENTRY( _start )
/*
MEMORY
{
flash1 (rxai!w) : ORIGIN = 0x10020400, LENGTH = 1k
flash2 (rxai!w) : ORIGIN = 0x10020810, LENGTH = 1k
flash3 (rxai!w) : ORIGIN = 0x10020c22, LENGTH = 1k
flash4 (rxai!w) : ORIGIN = 0x10021032, LENGTH = 1k
flash (rxai!w) : ORIGIN = 0x10021400, LENGTH = 150K
dram (wxa!ri) : ORIGIN = 0x10048000, LENGTH = 128K
iram (wxa!ri) : ORIGIN = 0x10068000, LENGTH = 32K
}*/
MEMORY
{
flash (rxai!w) : ORIGIN = 0x10000800, LENGTH = 150K
flash1 (rxai!w) : ORIGIN = 0x10045800, LENGTH = 1k
flash2 (rxai!w) : ORIGIN = 0x10045c10, LENGTH = 1k
flash3 (rxai!w) : ORIGIN = 0x10046022, LENGTH = 1k
flash4 (rxai!w) : ORIGIN = 0x10046432, LENGTH = 1k
dram (wxa!ri) : ORIGIN = 0x10048000, LENGTH = 128K
iram (wxa!ri) : ORIGIN = 0x10068000, LENGTH = 32K
}
SECTIONS
{
__main_stack_size = DEFINED(__main_stack_size) ? __main_stack_size : 2K;
__trap_stack_size = DEFINED(__trap_stack_size) ? __trap_stack_size : 2K;
.init :
{
KEEP (*(SORT_NONE(.init)))
} >flash AT>flash
.func1 :
{
*(.func1 .func1.*)
} >flash1 AT>flash1
.func2 :
{
*(.func2 .func2.*)
} >flash2 AT>flash2
.func3 :
{
*(.func3 .func3.*)
} >flash3 AT>flash3
.func4 :
{
*(.func4 .func4.*)
} >flash4 AT>flash4
.text :
{
. = ALIGN(160);
*(.text .text.*)
*(.gnu.linkonce.t.*)
} >flash AT>flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
} >flash AT>flash
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata :
{
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)
} >flash AT>flash
. = ALIGN(4);
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >flash AT>flash
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >flash AT>flash
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >flash AT>flash
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >flash AT>flash
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >flash AT>flash
.lalign :
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
} >flash AT>flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
} >dram AT>flash
.data :
{
*(.data .data.*)
*(.gnu.linkonce.d.*)
PROVIDE( _gp = . + 0x800 );
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >dram AT>flash
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
PROVIDE( _fbss = . );
PROVIDE( __bss_start = . );
.bss :
{
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
} >dram
. = ALIGN(8);
PROVIDE( _end = . );
PROVIDE( end = . );
PROVIDE( _heap_start = . );
.stack ORIGIN(dram) + LENGTH(dram) - (__main_stack_size + __trap_stack_size) :
{
PROVIDE( _heap_end = . );
. = __main_stack_size;
PROVIDE( _sp = . );
. = __trap_stack_size;
PROVIDE( _trap_sp = . );
} >dram
.ilalign :
{
. = ALIGN(4);
PROVIDE( _iram_lma = . );
} >flash AT>flash
.iram :
{
. = ALIGN(4);
PROVIDE( _iram_start = . );
*(.iram.entry*);
*(.iram*);
. = ALIGN(4);
PROVIDE( _iram_end = . );
} >iram AT>flash
.ilalign1 :
{
. = ALIGN(4);
PROVIDE( _flash_end = . );
} >flash AT>flash
}