#ifndef __MEM_CONFIG_H__ #define __MEM_CONFIG_H__ #include "iot_mem_org.h" //FLASH SIZE && PSRAM SIZE #define MEM_CFG_FLASH_SIZE (0x400000) #define MEM_CFG_PSRAM_SIZE (0x0) //FLASH LAYOUT //0x000000 ~ 0x020000 #define MEM_CFG_LAYOUT_SBL_OFFSET (0x00000000) #define MEM_CFG_LAYOUT_SBL_LENGTH (0xc000) //48k #define MEM_CFG_LAYOUT_DD1_OFFSET (0x0000c000) #define MEM_CFG_LAYOUT_DD1_LENGTH (0x2000) //8k #define MEM_CFG_LAYOUT_DD2_OFFSET (0x0000e000) #define MEM_CFG_LAYOUT_DD2_LENGTH (0x2000) //8k #define MEM_CFG_LAYOUT_PARAM_OFFSET (0x00010000) #define MEM_CFG_LAYOUT_PARAM_LENGTH (0x1000) //4k #define MEM_CFG_LAYOUT_OEM_OFFSET (0x00011000) #define MEM_CFG_LAYOUT_OEM_LENGTH (0x1000) //4k #define MEM_CFG_LAYOUT_PIB1_OFFSET (0x00012000) #define MEM_CFG_LAYOUT_PIB1_LENGTH (0x7000) //28k #define MEM_CFG_LAYOUT_PIB2_OFFSET (0x00019000) #define MEM_CFG_LAYOUT_PIB2_LENGTH (0x7000) //28k //0x300000 ~ 0x400000 #define MEM_CFG_LAYOUT_CUST_CUS_OFFSET (0x00300000) #define MEM_CFG_LAYOUT_CUST_CUS_LENGTH (0xdf000) //892k #define MEM_CFG_LAYOUT_CUST_PLC_OFFSET (0x003df000) #define MEM_CFG_LAYOUT_CUST_PLC_LENGTH (0x1f000) //124k #define MEM_CFG_LAYOUT_CALI_CUS_OFFSET (0x003fe000) #define MEM_CFG_LAYOUT_CALI_CUS_LENGTH (0x1000) //4k #define MEM_CFG_LAYOUT_CALI_PLC_OFFSET (0x003ff000) #define MEM_CFG_LAYOUT_CALI_PLC_LENGTH (0x1000) //4k //without psram #define MEM_CFG_LAYOUT_RUN_CUS_OFFSET (0x00020000) #define MEM_CFG_LAYOUT_RUN_CUS_LENGTH (0x40000) //256k #define MEM_CFG_LAYOUT_RUN_PLC_OFFSET (0x00060000) #define MEM_CFG_LAYOUT_RUN_PLC_LENGTH (0x120000) //1152k #define MEM_CFG_LAYOUT_FW1_CUS_OFFSET (0x00180000) #define MEM_CFG_LAYOUT_FW1_CUS_LENGTH (0x20000) //128k #define MEM_CFG_LAYOUT_FW1_PLC_OFFSET (0x001a0000) #define MEM_CFG_LAYOUT_FW1_PLC_LENGTH (0xa0000) //640k #define MEM_CFG_LAYOUT_FW2_CUS_OFFSET (0x00240000) #define MEM_CFG_LAYOUT_FW2_CUS_LENGTH (0x20000) //128k #define MEM_CFG_LAYOUT_FW2_PLC_OFFSET (0x00260000) #define MEM_CFG_LAYOUT_FW2_PLC_LENGTH (0xa0000) //640k #define MEM_CFG_LAYOUT_LOG1_OFFSET (0x00000000) #define MEM_CFG_LAYOUT_LOG1_LENGTH (0x0) //0k #define MEM_CFG_LAYOUT_LOG2_OFFSET (0x00000000) #define MEM_CFG_LAYOUT_LOG2_LENGTH (0x0) //0k #define MEM_CFG_CUS_FLASH_ADDRS (MEM_CFG_CHIP_ICACHE0_SFC_BASE + MEM_CFG_LAYOUT_RUN_CUS_OFFSET) #define MEM_CFG_CUS_FLASH_SIZE (MEM_CFG_LAYOUT_RUN_CUS_LENGTH) //256k #define MEM_CFG_CUS_DRAM_ADDRS (MEM_CFG_CHIP_DCACHE0_SMC_BASE) #define MEM_CFG_CUS_DRAM_SIZE (0x10000) //64k #define MEM_CFG_CUS_IRAM_ADDRS (MEM_CFG_CHIP_DCACHE1_SMC_BASE) #define MEM_CFG_CUS_IRAM_SIZE (0x8000) //32k #define MEM_CFG_PLC_FLASH_ADDRS (MEM_CFG_CHIP_ICACHE1_SFC_BASE + MEM_CFG_LAYOUT_RUN_PLC_OFFSET) #define MEM_CFG_PLC_FLASH_SIZE (MEM_CFG_LAYOUT_RUN_PLC_LENGTH) #define MEM_CFG_PLC_DRAM_ADDRS (MEM_CFG_CHIP_RAM_BASE + 0x800) #define MEM_CFG_PLC_DRAM_SIZE (0x5F800) //382k #define MEM_CFG_PLC_IRAM_ADDRS (MEM_CFG_CHIP_ICACHE2_SMC_BASE) #define MEM_CFG_PLC_IRAM_SIZE (0x80000) //32k //bbcpu fw //run addrs #define MEM_CFG_BBCPU_RUN_ADDRS (MEM_CFG_CHIP_RAM_BASE + 0x60000) #define MEM_CFG_BBCPU_RUN_SIZE (0xD000) //52k #define MEM_CFG_BBCPU_DRAM_ADDRS (MEM_CFG_CHIP_RAM_BASE + 0x6D000) #define MEM_CFG_BBCPU_DRAM_SIZE (0x3000) //12k //DCACHE used as heap #define MEM_CFG_HEAP1_ADDRS (MEM_CFG_CHIP_DCACHE0_SMC_BASE) #define MEM_CFG_HEAP1_SIZE (0x10000) //64k #define MEM_CFG_HEAP2_ADDRS (MEM_CFG_CHIP_DCACHE1_SMC_BASE) #define MEM_CFG_HEAP2_SIZE (0x10000) //64k #define MEM_CFG_HEAP_COUNT 2 #define MEM_CFG_HEAP_GROUP MEM_CFG_HEAP1_ADDRS, MEM_CFG_HEAP1_SIZE, \ MEM_CFG_HEAP2_ADDRS, MEM_CFG_HEAP2_SIZE //AUTHORITY FOR PARTITIONS #define MEM_CFG_AUTH_FOR_SBL (MEM_CFG_NONE(0) | MEM_CFG_NONE(1) | MEM_CFG_NONE(2)) #define MEM_CFG_AUTH_FOR_DD1 (MEM_CFG_NONE(0) | MEM_CFG_NONE(1) | MEM_CFG_NONE(2)) #define MEM_CFG_AUTH_FOR_DD2 (MEM_CFG_NONE(0) | MEM_CFG_NONE(1) | MEM_CFG_NONE(2)) #define MEM_CFG_AUTH_FOR_PARAM (MEM_CFG_RW(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2)) #define MEM_CFG_AUTH_FOR_OEM (MEM_CFG_R_ONLY(0) | MEM_CFG_R_ONLY(1) | MEM_CFG_R_ONLY(2)) #define MEM_CFG_AUTH_FOR_PIB1 (MEM_CFG_RW(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2)) #define MEM_CFG_AUTH_FOR_PIB2 (MEM_CFG_RW(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2)) #define MEM_CFG_AUTH_FOR_RUN_CUS (MEM_CFG_NONE(0) | MEM_CFG_NONE(1) | MEM_CFG_NONE(2)) #define MEM_CFG_AUTH_FOR_RUN_PLC (MEM_CFG_RW(0) | MEM_CFG_NONE(1) | MEM_CFG_NONE(2)) #define MEM_CFG_AUTH_FOR_FW1_CUS (MEM_CFG_RW(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2)) #define MEM_CFG_AUTH_FOR_FW1_PLC (MEM_CFG_RW(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2)) #define MEM_CFG_AUTH_FOR_FW2_CUS (MEM_CFG_RW(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2)) #define MEM_CFG_AUTH_FOR_FW2_PLC (MEM_CFG_RW(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2)) #define MEM_CFG_AUTH_FOR_CUS (MEM_CFG_RW(0) | MEM_CFG_R_ONLY(1) | MEM_CFG_R_ONLY(2)) #define MEM_CFG_AUTH_FOR_PLC (MEM_CFG_NONE(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2)) #define MEM_CFG_AUTH_FOR_CALI_CUS (MEM_CFG_RW(0) | MEM_CFG_R_ONLY(1) | MEM_CFG_R_ONLY(2)) #define MEM_CFG_AUTH_FOR_CALI_PLC (MEM_CFG_NONE(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2)) #define MEM_CFG_AUTH_FOR_LOG1 (MEM_CFG_RW(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2)) #define MEM_CFG_AUTH_FOR_LOG2 (MEM_CFG_RW(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2)) //PARTITIONS TABLE #define MEM_CFG_PARTITIONS {\ {MEM_CFG_PART_NUM_SBL, MEM_CFG_LAYOUT_SBL_OFFSET, MEM_CFG_LAYOUT_SBL_LENGTH,\ MEM_CFG_AUTH_FOR_SBL},\ {MEM_CFG_PART_NUM_DD1, MEM_CFG_LAYOUT_DD1_OFFSET, MEM_CFG_LAYOUT_DD1_LENGTH,\ MEM_CFG_AUTH_FOR_DD1},\ {MEM_CFG_PART_NUM_DD2, MEM_CFG_LAYOUT_DD2_OFFSET, MEM_CFG_LAYOUT_DD2_LENGTH,\ MEM_CFG_AUTH_FOR_DD2},\ {MEM_CFG_PART_NUM_PARAM, MEM_CFG_LAYOUT_PARAM_OFFSET, MEM_CFG_LAYOUT_PARAM_LENGTH,\ MEM_CFG_AUTH_FOR_PARAM},\ {MEM_CFG_PART_NUM_OEM, MEM_CFG_LAYOUT_OEM_OFFSET, MEM_CFG_LAYOUT_OEM_LENGTH,\ MEM_CFG_AUTH_FOR_OEM},\ {MEM_CFG_PART_NUM_PIB1, MEM_CFG_LAYOUT_PIB1_OFFSET, MEM_CFG_LAYOUT_PIB1_LENGTH,\ MEM_CFG_AUTH_FOR_PIB1},\ {MEM_CFG_PART_NUM_PIB2, MEM_CFG_LAYOUT_PIB2_OFFSET, MEM_CFG_LAYOUT_PIB2_LENGTH,\ MEM_CFG_AUTH_FOR_PIB2},\ {MEM_CFG_PART_NUM_CUS, MEM_CFG_LAYOUT_CUST_CUS_OFFSET, MEM_CFG_LAYOUT_CUST_CUS_LENGTH,\ MEM_CFG_AUTH_FOR_CUS},\ {MEM_CFG_PART_NUM_PLC, MEM_CFG_LAYOUT_CUST_PLC_OFFSET, MEM_CFG_LAYOUT_CUST_PLC_LENGTH,\ MEM_CFG_AUTH_FOR_PLC},\ {MEM_CFG_PART_NUM_CALI_CUS, MEM_CFG_LAYOUT_CALI_CUS_OFFSET, MEM_CFG_LAYOUT_CALI_CUS_LENGTH,\ MEM_CFG_AUTH_FOR_CALI_CUS},\ {MEM_CFG_PART_NUM_CALI_PLC, MEM_CFG_LAYOUT_CALI_PLC_OFFSET, MEM_CFG_LAYOUT_CALI_PLC_OFFSET,\ MEM_CFG_AUTH_FOR_CALI_PLC},\ {MEM_CFG_PART_NUM_RUN_CUS, MEM_CFG_LAYOUT_RUN_CUS_OFFSET, MEM_CFG_LAYOUT_RUN_CUS_LENGTH,\ MEM_CFG_AUTH_FOR_RUN_CUS},\ {MEM_CFG_PART_NUM_RUN_PLC, MEM_CFG_LAYOUT_RUN_PLC_OFFSET, MEM_CFG_LAYOUT_RUN_PLC_LENGTH,\ MEM_CFG_AUTH_FOR_RUN_PLC},\ {MEM_CFG_PART_NUM_FW1_CUS, MEM_CFG_LAYOUT_FW1_CUS_OFFSET, MEM_CFG_LAYOUT_FW1_CUS_LENGTH,\ MEM_CFG_AUTH_FOR_FW1_CUS},\ {MEM_CFG_PART_NUM_FW1_PLC, MEM_CFG_LAYOUT_FW1_PLC_OFFSET, MEM_CFG_LAYOUT_FW1_PLC_LENGTH,\ MEM_CFG_AUTH_FOR_FW1_PLC},\ {MEM_CFG_PART_NUM_FW2_CUS, MEM_CFG_LAYOUT_FW2_CUS_OFFSET, MEM_CFG_LAYOUT_FW2_CUS_LENGTH,\ MEM_CFG_AUTH_FOR_FW2_CUS},\ {MEM_CFG_PART_NUM_FW2_PLC, MEM_CFG_LAYOUT_FW2_PLC_OFFSET, MEM_CFG_LAYOUT_FW2_PLC_LENGTH,\ MEM_CFG_AUTH_FOR_FW2_PLC},\ {MEM_CFG_PART_NUM_LOG1, MEM_CFG_LAYOUT_LOG1_OFFSET, MEM_CFG_LAYOUT_LOG1_LENGTH,\ MEM_CFG_AUTH_FOR_LOG1},\ {MEM_CFG_PART_NUM_LOG2, MEM_CFG_LAYOUT_LOG2_OFFSET, MEM_CFG_LAYOUT_LOG2_LENGTH,\ MEM_CFG_AUTH_FOR_LOG2}\ } #endif