/**************************************************************************** * * Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED. * * This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT * be copied by any method or incorporated into another program without * the express written consent of Aerospace C.Power. This Information or any portion * thereof remains the property of Aerospace C.Power. The Information contained herein * is believed to be accurate and Aerospace C.Power assumes no responsibility or * liability for its use in any way and conveys no license or title under * any patent or copyright and makes no representation or warranty that this * Information is free from patent or copyright infringement. * * ****************************************************************************/ /* os shim includes */ #include "os_types.h" #include "os_task.h" #include "os_utils.h" /* common includes */ #include "iot_io.h" #include "iot_bitops.h" #include "iot_pkt.h" #include "iot_ipc.h" #include "iot_plc_lib.h" #include "iot_dbglog_api.h" #include "iot_config.h" /* driver includes */ #include "iot_clock.h" #include "iot_uart.h" /* cli includes */ #include "iot_cli.h" #include "iot_uart_h.h" /* debug includes*/ #include "dbg_io.h" #include "hw_reg_api.h" #include "uart.h" #include "apb_dma.h" #include "dma_hw.h" #include "hw_sadc.h" #include "sadc0_reg.h" #include "sadc1_reg.h" #include "sadc.h" #include "ahb_rf.h" #include "granite_reg.h" #include "ana.h" #include "apb_glb_reg.h" #include "phy_dfe_reg.h" #include "adc.h" #include "pmu_hw.h" desc_t *pdesc_rx=NULL; desc_t *pdesc_tx=NULL; desc_t *pdesc_rx_end=NULL; desc_t *pdesc_tx_end=NULL; void dma_desc_tail_exchange(desc_t*desc0, desc_t*desc1) { volatile unsigned int tail; tail = desc0->tail_lable[0]; desc0->tail_lable[0] = desc1->tail_lable[0]; desc1->tail_lable[0] = tail; } int int_stack[0x20]; void sadc_dma_handler(int device, int status) { desc_t *st, *end, *pnt; iot_pkt_t **pkt; static int int_stack_index=0; int_stack[(int_stack_index++)&0x1F] = status; if(DMA_INT_IN_SUC_EOF&status) { end = st = pdesc_rx_end; while((end->n_ptr != st) && (end->n_ptr->owner != DESC_OWNER_DMA)) end = end->n_ptr; pdesc_rx_end = end->n_ptr; pnt = pdesc_tx; while(st != end->n_ptr) { /* prepare pkt before exchange */ pkt = (iot_pkt_t**)EXTEN_POINTER(st); iot_pkt_set_tail(*pkt, (*pkt)->data + st->length); pkt = (iot_pkt_t**)EXTEN_POINTER(pnt); iot_pkt_set_data(*pkt, (*pkt)->head); iot_pkt_set_tail(*pkt, (*pkt)->head); dma_desc_tail_exchange(pnt, st); pkt = (iot_pkt_t**)EXTEN_POINTER(st); DMA_MAKE_DESC(st, (*pkt)->data, TEST_BUF_SIZE, 0, 0, 0, 0, DESC_OWNER_DMA); /* send pkt recieved */ pkt = (iot_pkt_t**)EXTEN_POINTER(pnt); DMA_MAKE_DESC(pnt, (*pkt)->data, TEST_BUF_SIZE, iot_pkt_block_len(*pkt, IOT_PKT_BLOCK_DATA),\ 0, 0, 0, DESC_OWNER_DMA); st = st->n_ptr; pnt = pnt->n_ptr; } end = pnt->l_ptr; end->n_ptr = NULL; pdesc_tx_end->n_ptr = pdesc_tx; if(DESC_OWNER_CPU == pdesc_tx_end->owner) { dma_hw_start_send(DMA_TEST_DEVICE, pdesc_tx); } pdesc_tx = pnt; pdesc_tx_end = end; } return ; } #if DT_SADC_POLLING_EN /* 7 phase data */ uint32_t chn_data[DT_SADC_SAMPLE_PHASE_NUM][DT_SADC_SAMPLE_QUANTITY] = {0}; #if DT_SADC_TEST_MODE == DT_SADC_DUAL_13PHASE_MODE uint32_t chn_data1[DT_SADC_SAMPLE_PHASE_NUM - 1][DT_SADC_SAMPLE_QUANTITY] = {0}; #endif void sadc_data_polling() { uint32_t count0 = 0, count1 = 0, count2 = 0, \ count30 = 0, count31 = 0, count32 = 0, count33 = 0; while(1) { if (count0= DT_SADC_DUAL_7PHASE_MODE sadc_multi_phase_test(); #else /* voltage or current mode */ sadc_single_phase_test(); #endif } #else #include "dma_hw_rf.h" #include "apb.h" extern void dma_hw_rst(); extern void dma_hw_fsm_rst(); void sadc_desc_data_process( uint32_t desc_addr, uint32_t buf_addr, bool_t loop_en) { volatile uint32_t tmp = 0; volatile bool_t done_flag = false; volatile int32_t sample_tmp = 0; volatile uint32_t i = 0; /* wait desc1 done */ do { tmp = SOC_READ_REG(desc_addr) & 0x40000000; done_flag = tmp >> 30; } while (done_flag == 0); if (loop_en) { /* clr owner */ SOC_WRITE_REG(desc_addr, \ (1 << 31) | \ (0 << 24) | \ (0xFFC << 12) | \ (0xFFC << 0)); } for (i = 0; i < (0xFFC >> 2); i++) { tmp = SOC_READ_REG(buf_addr + (i << 2)) & 0xfffff; if (tmp & 0x80000) { sample_tmp = tmp - 0x100000; } else { sample_tmp = tmp; } /* print will block dma */ if (!loop_en) { iot_printf("%d\n", sample_tmp); } } iot_printf("%d\n", 2500); } void sadc_test_task(void) { volatile uint32_t tmp = 0; volatile bool_t loop_flag = false; int cnt = 0; desc_t *rx = NULL; const int desc_size = sizeof(desc_t); /* apb enable */ apb_enable(APB_DMA_HW); /* dma reset */ dma_hw_rst(); dma_hw_fsm_rst(); /* adc init */ sadc_init(ANA_SADC0, NULL); /* channel and phase init */ /* 1 phase mode, only phase 0*/ sadc_phase_mode_set(ANA_SADC0, 0); sadc_phase_sel(ANA_SADC0, 0); sadc_phase_sel_scl_mux(0, 0 + SADC_CHANNEL_EXT); sadc_adc_gain_set(0, 0); /* mtr sel scl from Meter or vtemp/vcm */ sadc_mtr_sel_scl_mux(0, 0); /* start en */ sadc_start_en(ANA_SADC0, 1); /* sel scl */ sadc_phase_sel_scl_mux(0, SADC_TSW_SEL_SCL_MUX_DIFF_CH10); /* enable AI ram */ tmp = SOC_READ_REG(0x50000008); SOC_WRITE_REG(0x50000008, tmp | 0x80); /* alloc mem for desc */ pdesc_rx = (desc_t *)os_mem_malloc(0, TEST_DESC_NUM * desc_size); /* check alloc result */ if (NULL == pdesc_rx) { return ; } rx = pdesc_rx; /* To fill descriptors */ for(cnt = 0; cnt < TEST_DESC_NUM; cnt++) { /* for RX */ DMA_MAKE_DESC(rx, \ 0x73fd0000 + cnt * 0x10000, \ 0xFFC, \ 0xFFC, \ 0, \ 0, \ 0, \ DESC_OWNER_DMA); rx->n_ptr = (desc_t*)((int)rx + desc_size); rx->l_ptr = (desc_t*)((int)rx - desc_size); rx = (desc_t*)((int)rx + desc_size); } rx = (desc_t*)((int)pdesc_rx + desc_size*(TEST_DESC_NUM-1)); pdesc_rx->l_ptr = rx; rx->n_ptr = pdesc_rx; pdesc_rx_end = pdesc_rx; /* soc rx link */ DMA_HW_RF_WRITE_REG(CFG_DMA_HW_RX_CHN12_CFG0_ADDR, (uint32_t)pdesc_rx); /* start */ tmp = DMA_HW_RF_READ_REG(CFG_DMA_HW_RX_CHN12_CFG1_ADDR); REG_FIELD_SET(CHN12_RX_START, tmp, 1); DMA_HW_RF_WRITE_REG(CFG_DMA_HW_RX_CHN12_CFG1_ADDR, tmp); while(1) { for(cnt = 0; cnt < TEST_DESC_NUM; cnt++) { /* data process */ sadc_desc_data_process( \ (uint32_t)pdesc_rx, \ 0x73fd0000 + cnt * 0x10000, \ loop_flag); } while(!loop_flag); } } #endif