//-----------------------------------
#define CFG_BB_TEST_ONLY_ADDR 0x0000

//-----------------------------------
#define CFG_BB_DB_AMP_CTRL_ADDR 0x0004
#define SW_PWR_BACKOFF_16QAM_OFFSET 16
#define SW_PWR_BACKOFF_16QAM_MASK 0x000F0000
#define SW_PWR_BACKOFF_QPSK_OFFSET 12
#define SW_PWR_BACKOFF_QPSK_MASK 0x0000F000
#define SW_DB_UP_AMP_PARA_INT_OFFSET 2
#define SW_DB_UP_AMP_PARA_INT_MASK 0x000001FC
#define SW_DB_UP_AMP_PARA_FRAC_OFFSET 0
#define SW_DB_UP_AMP_PARA_FRAC_MASK 0x00000003

//-----------------------------------
#define CFG_BB_TX_IFFT_CTRL_ADDR 0x0008
#define SW_IFFT_TD_BIT_SEL_OFFSET 0
#define SW_IFFT_TD_BIT_SEL_MASK 0x00000007

//-----------------------------------
#define CFG_BB_TX_TURBO_SET_ADDR 0x000C
#define SW_TX_SCRAMBLE_BASED_PPDU_OFFSET 2
#define SW_TX_SCRAMBLE_BASED_PPDU_MASK 0x00000004
#define SW_SCRAMBLE_RESET_MODE_OFFSET 1
#define SW_SCRAMBLE_RESET_MODE_MASK 0x00000002
#define SW_SCRAMBLE_MODE_OFFSET 0
#define SW_SCRAMBLE_MODE_MASK 0x00000001

//HW module read/write macro
#define PHY_TX_READ_REG(addr) SOC_READ_REG(PHY_TX_BASEADDR + addr)
#define PHY_TX_WRITE_REG(addr,value) SOC_WRITE_REG(PHY_TX_BASEADDR + addr,value)