//-----------------------------------
#define CFG_AUDIO_FFT_RVER_ADDR 0x0000
#define AUDIO_FFT_VER_OFFSET 0
#define AUDIO_FFT_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_AUDIO_FFT_CMD_ADDR 0x0004
#define SW_FFT_DONE_OFFSET 1
#define SW_FFT_DONE_MASK 0x00000002
#define SW_FFT_START_OFFSET 0
#define SW_FFT_START_MASK 0x00000001

//-----------------------------------
#define CFG_AUDIO_FFT_CFG_ADDR 0x0008
#define SW_FLT_RND_SEL_OFFSET 14
#define SW_FLT_RND_SEL_MASK 0x0001C000
#define SW_IS_SIGNED_EXT_OFFSET 13
#define SW_IS_SIGNED_EXT_MASK 0x00002000
#define SW_DATA_MODE_OFFSET 10
#define SW_DATA_MODE_MASK 0x00001C00
#define SW_DBG_ON_OFFSET 8
#define SW_DBG_ON_MASK 0x00000100
#define SW_CLK_FORCE_ON_OFFSET 7
#define SW_CLK_FORCE_ON_MASK 0x00000080
#define SW_IGNORE_FLT2I_ST_OFFSET 6
#define SW_IGNORE_FLT2I_ST_MASK 0x00000040
#define SW_ST_CLR_OFFSET 5
#define SW_ST_CLR_MASK 0x00000020
#define SW_IS_COMPLEX_OFFSET 4
#define SW_IS_COMPLEX_MASK 0x00000010
#define SW_IS_FFT_OFFSET 3
#define SW_IS_FFT_MASK 0x00000008
#define SW_FFT_SIZE_OFFSET 0
#define SW_FFT_SIZE_MASK 0x00000007

//-----------------------------------
#define CFG_AUDIO_FFT_SHIFT_ADDR 0x000C
#define SW_IN_LSH_BIT_SEL_OFFSET 13
#define SW_IN_LSH_BIT_SEL_MASK 0x00006000
#define SW_OUT_RSH_BIT_SEL_OFFSET 10
#define SW_OUT_RSH_BIT_SEL_MASK 0x00001C00
#define SW_FFT_STAGE4_SHIFT_OFFSET 8
#define SW_FFT_STAGE4_SHIFT_MASK 0x00000300
#define SW_FFT_STAGE3_SHIFT_OFFSET 6
#define SW_FFT_STAGE3_SHIFT_MASK 0x000000C0
#define SW_FFT_STAGE2_SHIFT_OFFSET 4
#define SW_FFT_STAGE2_SHIFT_MASK 0x00000030
#define SW_FFT_STAGE1_SHIFT_OFFSET 2
#define SW_FFT_STAGE1_SHIFT_MASK 0x0000000C
#define SW_FFT_STAGE0_SHIFT_OFFSET 0
#define SW_FFT_STAGE0_SHIFT_MASK 0x00000003

//-----------------------------------
#define CFG_AUDIO_FLT_CFG_ADDR 0x0010
#define SW_I2FLT_ST_OFFSET 24
#define SW_I2FLT_ST_MASK 0xFF000000
#define SW_FLT2I_ST_OFFSET 16
#define SW_FLT2I_ST_MASK 0x00FF0000
#define SW_FLTOUT_EXP_BIAS_OFFSET 8
#define SW_FLTOUT_EXP_BIAS_MASK 0x0000FF00
#define SW_FLTIN_EXP_BIAS_OFFSET 0
#define SW_FLTIN_EXP_BIAS_MASK 0x000000FF

//-----------------------------------
#define CFG_FLT2I_REG0_ADDR 0x0020
#define SW_FLT2I_REG0_OFFSET 0
#define SW_FLT2I_REG0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_FLT2I_REG1_ADDR 0x0024
#define SW_FLT2I_REG1_OFFSET 0
#define SW_FLT2I_REG1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_FLT2I_REG2_ADDR 0x0028
#define SW_FLT2I_REG2_OFFSET 0
#define SW_FLT2I_REG2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_FLT2I_REG3_ADDR 0x002C
#define SW_FLT2I_REG3_OFFSET 0
#define SW_FLT2I_REG3_MASK 0xFFFFFFFF

//HW module read/write macro
#define AUDIO_FFT_RF0_READ_REG(addr) SOC_READ_REG(AUDIO_FFT_RF0_BASEADDR + addr)
#define AUDIO_FFT_RF0_WRITE_REG(addr,value) SOC_WRITE_REG(AUDIO_FFT_RF0_BASEADDR + addr,value)
#define AUDIO_FFT_RF1_READ_REG(addr) SOC_READ_REG(AUDIO_FFT_RF1_BASEADDR + addr)
#define AUDIO_FFT_RF1_WRITE_REG(addr,value) SOC_WRITE_REG(AUDIO_FFT_RF1_BASEADDR + addr,value)