//----------------------------------- #define CFG_CNN_CMD_ADDR 0x0 #define CNN_CMD_OFFSET 0 #define CNN_CMD_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_DMA_EXT_CFG_START_ADDRESS_ADDR 0x4 #define DMA_EXT_CFG_START_ADDRESS_OFFSET 5 #define DMA_EXT_CFG_START_ADDRESS_MASK 0xFFFFFFE0 //----------------------------------- #define CFG_CNN_MEM_BLOCK_BANK_SWITCH_ADDR 0xC #define MEM_BLOCK_BANK_SWITCH_OFFSET 0 #define MEM_BLOCK_BANK_SWITCH_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CNN_INT_STATUS_ADDR 0x10 #define CNN_ALL_DONE_RAW_INT_STATUS_OFFSET 31 #define CNN_ALL_DONE_RAW_INT_STATUS_MASK 0x80000000 #define CNN_LL_RAW_INT_STATUS_OFFSET 30 #define CNN_LL_RAW_INT_STATUS_MASK 0x40000000 #define CNN_3D_DONE_RAW_INT_STATUS_OFFSET 29 #define CNN_3D_DONE_RAW_INT_STATUS_MASK 0x20000000 #define CNN_2D_DONE_RAW_INT_STATUS_OFFSET 28 #define CNN_2D_DONE_RAW_INT_STATUS_MASK 0x10000000 #define CNN_1D_DONE_RAW_INT_STATUS_OFFSET 27 #define CNN_1D_DONE_RAW_INT_STATUS_MASK 0x08000000 #define CNN_ELEM_DONE_RAW_INT_STATUS_OFFSET 26 #define CNN_ELEM_DONE_RAW_INT_STATUS_MASK 0x04000000 #define CNN_3D_START_RAW_INT_STATUS_OFFSET 25 #define CNN_3D_START_RAW_INT_STATUS_MASK 0x02000000 #define CNN_2D_START_RAW_INT_STATUS_OFFSET 24 #define CNN_2D_START_RAW_INT_STATUS_MASK 0x01000000 #define CNN_FSM_FI_DMA_REQ_RAW_INT_STATUS_OFFSET 23 #define CNN_FSM_FI_DMA_REQ_RAW_INT_STATUS_MASK 0x00800000 #define CNN_FSM_WI_DMA_REQ_RAW_INT_STATUS_OFFSET 22 #define CNN_FSM_WI_DMA_REQ_RAW_INT_STATUS_MASK 0x00400000 #define CNN_GROUP_DONE_RAW_INT_STATUS_OFFSET 21 #define CNN_GROUP_DONE_RAW_INT_STATUS_MASK 0x00200000 #define CNN_LL_NUM_DONE_RAW_INT_STATUS_OFFSET 20 #define CNN_LL_NUM_DONE_RAW_INT_STATUS_MASK 0x00100000 #define CNN_DMA_CFG_DONE_RAW_INT_STATUS_OFFSET 19 #define CNN_DMA_CFG_DONE_RAW_INT_STATUS_MASK 0x00080000 #define CNN_DMA_FO_INT_DONE_STATUS_OFFSET 18 #define CNN_DMA_FO_INT_DONE_STATUS_MASK 0x00040000 #define CNN_DMA_FI_INT_DONE_STATUS_OFFSET 17 #define CNN_DMA_FI_INT_DONE_STATUS_MASK 0x00020000 #define CNN_DMA_WI_INT_DONE_STATUS_OFFSET 16 #define CNN_DMA_WI_INT_DONE_STATUS_MASK 0x00010000 #define CNN_GROUP_CNT7_DONE_RAW_INT_STATUS_OFFSET 15 #define CNN_GROUP_CNT7_DONE_RAW_INT_STATUS_MASK 0x00008000 #define CNN_GROUP_CNT6_DONE_RAW_INT_STATUS_OFFSET 14 #define CNN_GROUP_CNT6_DONE_RAW_INT_STATUS_MASK 0x00004000 #define CNN_GROUP_CNT5_DONE_RAW_INT_STATUS_OFFSET 13 #define CNN_GROUP_CNT5_DONE_RAW_INT_STATUS_MASK 0x00002000 #define CNN_GROUP_CNT4_DONE_RAW_INT_STATUS_OFFSET 12 #define CNN_GROUP_CNT4_DONE_RAW_INT_STATUS_MASK 0x00001000 #define CNN_GROUP_CNT3_DONE_RAW_INT_STATUS_OFFSET 11 #define CNN_GROUP_CNT3_DONE_RAW_INT_STATUS_MASK 0x00000800 #define CNN_GROUP_CNT2_DONE_RAW_INT_STATUS_OFFSET 10 #define CNN_GROUP_CNT2_DONE_RAW_INT_STATUS_MASK 0x00000400 #define CNN_GROUP_CNT1_DONE_RAW_INT_STATUS_OFFSET 9 #define CNN_GROUP_CNT1_DONE_RAW_INT_STATUS_MASK 0x00000200 #define CNN_GROUP_CNT0_DONE_RAW_INT_STATUS_OFFSET 8 #define CNN_GROUP_CNT0_DONE_RAW_INT_STATUS_MASK 0x00000100 #define CNN_LL_CNT7_DONE_RAW_INT_STATUS_OFFSET 7 #define CNN_LL_CNT7_DONE_RAW_INT_STATUS_MASK 0x00000080 #define CNN_LL_CNT6_DONE_RAW_INT_STATUS_OFFSET 6 #define CNN_LL_CNT6_DONE_RAW_INT_STATUS_MASK 0x00000040 #define CNN_LL_CNT5_DONE_RAW_INT_STATUS_OFFSET 5 #define CNN_LL_CNT5_DONE_RAW_INT_STATUS_MASK 0x00000020 #define CNN_LL_CNT4_DONE_RAW_INT_STATUS_OFFSET 4 #define CNN_LL_CNT4_DONE_RAW_INT_STATUS_MASK 0x00000010 #define CNN_LL_CNT3_DONE_RAW_INT_STATUS_OFFSET 3 #define CNN_LL_CNT3_DONE_RAW_INT_STATUS_MASK 0x00000008 #define CNN_LL_CNT2_DONE_RAW_INT_STATUS_OFFSET 2 #define CNN_LL_CNT2_DONE_RAW_INT_STATUS_MASK 0x00000004 #define CNN_LL_CNT1_DONE_RAW_INT_STATUS_OFFSET 1 #define CNN_LL_CNT1_DONE_RAW_INT_STATUS_MASK 0x00000002 #define CNN_LL_CNT0_DONE_RAW_INT_STATUS_OFFSET 0 #define CNN_LL_CNT0_DONE_RAW_INT_STATUS_MASK 0x00000001 //----------------------------------- #define CFG_CNN_INT_CLR_ADDR 0x14 #define CNN_ALL_DONE_RAW_INT_CLR_OFFSET 31 #define CNN_ALL_DONE_RAW_INT_CLR_MASK 0x80000000 #define CNN_LL_RAW_INT_CLR_OFFSET 30 #define CNN_LL_RAW_INT_CLR_MASK 0x40000000 #define CNN_3D_DONE_RAW_INT_CLR_OFFSET 29 #define CNN_3D_DONE_RAW_INT_CLR_MASK 0x20000000 #define CNN_2D_DONE_RAW_INT_CLR_OFFSET 28 #define CNN_2D_DONE_RAW_INT_CLR_MASK 0x10000000 #define CNN_1D_DONE_RAW_INT_CLR_OFFSET 27 #define CNN_1D_DONE_RAW_INT_CLR_MASK 0x08000000 #define CNN_ELEM_DONE_RAW_INT_CLR_OFFSET 26 #define CNN_ELEM_DONE_RAW_INT_CLR_MASK 0x04000000 #define CNN_3D_START_RAW_INT_CLR_OFFSET 25 #define CNN_3D_START_RAW_INT_CLR_MASK 0x02000000 #define CNN_2D_START_RAW_INT_CLR_OFFSET 24 #define CNN_2D_START_RAW_INT_CLR_MASK 0x01000000 #define CNN_FSM_FI_DMA_REQ_RAW_INT_CLR_OFFSET 23 #define CNN_FSM_FI_DMA_REQ_RAW_INT_CLR_MASK 0x00800000 #define CNN_FSM_WI_DMA_REQ_RAW_INT_CLR_OFFSET 22 #define CNN_FSM_WI_DMA_REQ_RAW_INT_CLR_MASK 0x00400000 #define CNN_GROUP_DONE_RAW_INT_CLR_OFFSET 21 #define CNN_GROUP_DONE_RAW_INT_CLR_MASK 0x00200000 #define CNN_LL_NUM_DONE_RAW_INT_CLR_OFFSET 20 #define CNN_LL_NUM_DONE_RAW_INT_CLR_MASK 0x00100000 #define CNN_DMA_CFG_DONE_RAW_INT_CLR_OFFSET 19 #define CNN_DMA_CFG_DONE_RAW_INT_CLR_MASK 0x00080000 #define CNN_DMA_FO_INT_DONE_CLR_OFFSET 18 #define CNN_DMA_FO_INT_DONE_CLR_MASK 0x00040000 #define CNN_DMA_FI_INT_DONE_CLR_OFFSET 17 #define CNN_DMA_FI_INT_DONE_CLR_MASK 0x00020000 #define CNN_DMA_WI_INT_DONE_CLR_OFFSET 16 #define CNN_DMA_WI_INT_DONE_CLR_MASK 0x00010000 #define CNN_GROUP_CNT7_DONE_RAW_INT_CLR_OFFSET 15 #define CNN_GROUP_CNT7_DONE_RAW_INT_CLR_MASK 0x00008000 #define CNN_GROUP_CNT6_DONE_RAW_INT_CLR_OFFSET 14 #define CNN_GROUP_CNT6_DONE_RAW_INT_CLR_MASK 0x00004000 #define CNN_GROUP_CNT5_DONE_RAW_INT_CLR_OFFSET 13 #define CNN_GROUP_CNT5_DONE_RAW_INT_CLR_MASK 0x00002000 #define CNN_GROUP_CNT4_DONE_RAW_INT_CLR_OFFSET 12 #define CNN_GROUP_CNT4_DONE_RAW_INT_CLR_MASK 0x00001000 #define CNN_GROUP_CNT3_DONE_RAW_INT_CLR_OFFSET 11 #define CNN_GROUP_CNT3_DONE_RAW_INT_CLR_MASK 0x00000800 #define CNN_GROUP_CNT2_DONE_RAW_INT_CLR_OFFSET 10 #define CNN_GROUP_CNT2_DONE_RAW_INT_CLR_MASK 0x00000400 #define CNN_GROUP_CNT1_DONE_RAW_INT_CLR_OFFSET 9 #define CNN_GROUP_CNT1_DONE_RAW_INT_CLR_MASK 0x00000200 #define CNN_GROUP_CNT0_DONE_RAW_INT_CLR_OFFSET 8 #define CNN_GROUP_CNT0_DONE_RAW_INT_CLR_MASK 0x00000100 #define CNN_LL_CNT7_DONE_RAW_INT_CLR_OFFSET 7 #define CNN_LL_CNT7_DONE_RAW_INT_CLR_MASK 0x00000080 #define CNN_LL_CNT6_DONE_RAW_INT_CLR_OFFSET 6 #define CNN_LL_CNT6_DONE_RAW_INT_CLR_MASK 0x00000040 #define CNN_LL_CNT5_DONE_RAW_INT_CLR_OFFSET 5 #define CNN_LL_CNT5_DONE_RAW_INT_CLR_MASK 0x00000020 #define CNN_LL_CNT4_DONE_RAW_INT_CLR_OFFSET 4 #define CNN_LL_CNT4_DONE_RAW_INT_CLR_MASK 0x00000010 #define CNN_LL_CNT3_DONE_RAW_INT_CLR_OFFSET 3 #define CNN_LL_CNT3_DONE_RAW_INT_CLR_MASK 0x00000008 #define CNN_LL_CNT2_DONE_RAW_INT_CLR_OFFSET 2 #define CNN_LL_CNT2_DONE_RAW_INT_CLR_MASK 0x00000004 #define CNN_LL_CNT1_DONE_RAW_INT_CLR_OFFSET 1 #define CNN_LL_CNT1_DONE_RAW_INT_CLR_MASK 0x00000002 #define CNN_LL_CNT0_DONE_RAW_INT_CLR_OFFSET 0 #define CNN_LL_CNT0_DONE_RAW_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_DEBUG_EN_ADDR 0x18 #define CNN_GROUP_DONE_HALT_NUM_OFFSET 16 #define CNN_GROUP_DONE_HALT_NUM_MASK 0xFFFF0000 #define DEBUG_BUS_SEL_OFFSET 8 #define DEBUG_BUS_SEL_MASK 0x0000FF00 #define SW_HALT_REQ_OFFSET 0 #define SW_HALT_REQ_MASK 0x00000001 //----------------------------------- #define CFG_DEBUG_INFO0_ADDR 0x20 #define CNN_SCH_DEBUG_INFO_OFFSET 0 #define CNN_SCH_DEBUG_INFO_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DEBUG_INFO1_ADDR 0x24 #define CNN_DMA_EMC_DEBUG_INFO_OFFSET 0 #define CNN_DMA_EMC_DEBUG_INFO_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DEBUG_INFO2_ADDR 0x28 #define CNN_FSM_DEBUG_INFO0_OFFSET 0 #define CNN_FSM_DEBUG_INFO0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DEBUG_INFO3_ADDR 0x2C #define CNN_FSM_DEBUG_INFO1_OFFSET 0 #define CNN_FSM_DEBUG_INFO1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DEBUG_INFO4_ADDR 0x30 #define CNN_FSM_DEBUG_INFO2_OFFSET 0 #define CNN_FSM_DEBUG_INFO2_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DEBUG_INFO5_ADDR 0x34 #define CNN_CAL_CNT_OFFSET 0 #define CNN_CAL_CNT_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DEBUG_INFO6_ADDR 0x38 #define CNN_TRANS_CNT_OFFSET 0 #define CNN_TRANS_CNT_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DNN_ITEM_TIMES_ADDR 0x40 #define DNN_BIAS_EN_OFFSET 16 #define DNN_BIAS_EN_MASK 0xFFFF0000 #define DNN_PRE_PROCESS_EN_OFFSET 8 #define DNN_PRE_PROCESS_EN_MASK 0x00000100 #define DNN_ITEM_TIMES_OFFSET 0 #define DNN_ITEM_TIMES_MASK 0x0000000F //----------------------------------- #define CFG_DNN_SIGMOID_EN_ADDR 0x44 #define DNN_SOFTMAX_EN_OFFSET 16 #define DNN_SOFTMAX_EN_MASK 0xFFFF0000 #define DNN_SIGMOID_EN_OFFSET 0 #define DNN_SIGMOID_EN_MASK 0x0000FFFF //----------------------------------- #define CFG_DNN_MATRIX0_SCALE_ADDR 0x48 #define DNN_MATRIX0_N_OFFSET 16 #define DNN_MATRIX0_N_MASK 0xFFFF0000 #define DNN_MATRIX0_M_OFFSET 0 #define DNN_MATRIX0_M_MASK 0x0000FFFF //----------------------------------- #define CFG_DNN_MATRIX1_SCALE_ADDR 0x4C #define DNN_MATRIX1_N_OFFSET 16 #define DNN_MATRIX1_N_MASK 0xFFFF0000 #define DNN_MATRIX1_M_OFFSET 0 #define DNN_MATRIX1_M_MASK 0x0000FFFF //----------------------------------- #define CFG_DNN_MATRIX2_SCALE_ADDR 0x50 #define DNN_MATRIX2_N_OFFSET 16 #define DNN_MATRIX2_N_MASK 0xFFFF0000 #define DNN_MATRIX2_M_OFFSET 0 #define DNN_MATRIX2_M_MASK 0x0000FFFF //----------------------------------- #define CFG_DNN_MATRIX3_SCALE_ADDR 0x54 #define DNN_MATRIX3_N_OFFSET 16 #define DNN_MATRIX3_N_MASK 0xFFFF0000 #define DNN_MATRIX3_M_OFFSET 0 #define DNN_MATRIX3_M_MASK 0x0000FFFF //----------------------------------- #define CFG_DNN_MATRIX4_SCALE_ADDR 0x58 #define DNN_MATRIX4_N_OFFSET 16 #define DNN_MATRIX4_N_MASK 0xFFFF0000 #define DNN_MATRIX4_M_OFFSET 0 #define DNN_MATRIX4_M_MASK 0x0000FFFF //----------------------------------- #define CFG_DNN_MATRIX5_SCALE_ADDR 0x5C #define DNN_MATRIX5_N_OFFSET 16 #define DNN_MATRIX5_N_MASK 0xFFFF0000 #define DNN_MATRIX5_M_OFFSET 0 #define DNN_MATRIX5_M_MASK 0x0000FFFF //----------------------------------- #define CFG_DNN_MATRIX6_SCALE_ADDR 0x60 #define DNN_MATRIX6_N_OFFSET 16 #define DNN_MATRIX6_N_MASK 0xFFFF0000 #define DNN_MATRIX6_M_OFFSET 0 #define DNN_MATRIX6_M_MASK 0x0000FFFF //----------------------------------- #define CFG_DNN_MATRIX7_SCALE_ADDR 0x64 #define DNN_MATRIX7_N_OFFSET 16 #define DNN_MATRIX7_N_MASK 0xFFFF0000 #define DNN_MATRIX7_M_OFFSET 0 #define DNN_MATRIX7_M_MASK 0x0000FFFF //----------------------------------- #define CFG_DNN_MATRIX8_SCALE_ADDR 0x68 #define DNN_MATRIX8_N_OFFSET 16 #define DNN_MATRIX8_N_MASK 0xFFFF0000 #define DNN_MATRIX8_M_OFFSET 0 #define DNN_MATRIX8_M_MASK 0x0000FFFF //----------------------------------- #define CFG_DNN_MATRIX9_SCALE_ADDR 0x6C #define DNN_MATRIX9_N_OFFSET 16 #define DNN_MATRIX9_N_MASK 0xFFFF0000 #define DNN_MATRIX9_M_OFFSET 0 #define DNN_MATRIX9_M_MASK 0x0000FFFF //----------------------------------- #define CFG_DNN_MATRIX10_SCALE_ADDR 0x70 #define DNN_MATRIX10_N_OFFSET 16 #define DNN_MATRIX10_N_MASK 0xFFFF0000 #define DNN_MATRIX10_M_OFFSET 0 #define DNN_MATRIX10_M_MASK 0x0000FFFF //----------------------------------- #define CFG_DNN_MATRIX11_SCALE_ADDR 0x74 #define DNN_MATRIX11_N_OFFSET 16 #define DNN_MATRIX11_N_MASK 0xFFFF0000 #define DNN_MATRIX11_M_OFFSET 0 #define DNN_MATRIX11_M_MASK 0x0000FFFF //----------------------------------- #define CFG_DNN_MATRIX12_SCALE_ADDR 0x78 #define DNN_MATRIX12_N_OFFSET 16 #define DNN_MATRIX12_N_MASK 0xFFFF0000 #define DNN_MATRIX12_M_OFFSET 0 #define DNN_MATRIX12_M_MASK 0x0000FFFF //----------------------------------- #define CFG_DNN_MATRIX13_SCALE_ADDR 0x7C #define DNN_MATRIX13_N_OFFSET 16 #define DNN_MATRIX13_N_MASK 0xFFFF0000 #define DNN_MATRIX13_M_OFFSET 0 #define DNN_MATRIX13_M_MASK 0x0000FFFF //----------------------------------- #define CFG_DNN_MATRIX14_SCALE_ADDR 0x80 #define DNN_MATRIX14_N_OFFSET 16 #define DNN_MATRIX14_N_MASK 0xFFFF0000 #define DNN_MATRIX14_M_OFFSET 0 #define DNN_MATRIX14_M_MASK 0x0000FFFF //----------------------------------- #define CFG_DNN_MATRIX15_SCALE_ADDR 0x84 #define DNN_MATRIX15_N_OFFSET 16 #define DNN_MATRIX15_N_MASK 0xFFFF0000 #define DNN_MATRIX15_M_OFFSET 0 #define DNN_MATRIX15_M_MASK 0x0000FFFF //----------------------------------- #define CFG_DNN_SHIFT_NUM_W0_ADDR 0x88 #define DNN_SHIFT_NUM_ITEM0_OFFSET 0 #define DNN_SHIFT_NUM_ITEM0_MASK 0x000000FF #define DNN_BIAS_SHIFT_NUM_ITEM0_OFFSET 8 #define DNN_BIAS_SHIFT_NUM_ITEM0_MASK 0x0000FF00 #define DNN_SHIFT_NUM_ITEM1_OFFSET 16 #define DNN_SHIFT_NUM_ITEM1_MASK 0x00FF0000 #define DNN_BIAS_SHIFT_NUM_ITEM1_OFFSET 24 #define DNN_BIAS_SHIFT_NUM_ITEM1_MASK 0xFF000000 //----------------------------------- #define CFG_DNN_SHIFT_NUM_W1_ADDR 0x8C #define DNN_SHIFT_NUM_ITEM2_OFFSET 0 #define DNN_SHIFT_NUM_ITEM2_MASK 0x000000FF #define DNN_BIAS_SHIFT_NUM_ITEM2_OFFSET 8 #define DNN_BIAS_SHIFT_NUM_ITEM2_MASK 0x0000FF00 #define DNN_SHIFT_NUM_ITEM3_OFFSET 16 #define DNN_SHIFT_NUM_ITEM3_MASK 0x00FF0000 #define DNN_BIAS_SHIFT_NUM_ITEM3_OFFSET 24 #define DNN_BIAS_SHIFT_NUM_ITEM3_MASK 0xFF000000 //----------------------------------- #define CFG_DNN_SHIFT_NUM_W2_ADDR 0x90 #define DNN_SHIFT_NUM_ITEM4_OFFSET 0 #define DNN_SHIFT_NUM_ITEM4_MASK 0x000000FF #define DNN_BIAS_SHIFT_NUM_ITEM4_OFFSET 8 #define DNN_BIAS_SHIFT_NUM_ITEM4_MASK 0x0000FF00 #define DNN_SHIFT_NUM_ITEM5_OFFSET 16 #define DNN_SHIFT_NUM_ITEM5_MASK 0x00FF0000 #define DNN_BIAS_SHIFT_NUM_ITEM5_OFFSET 24 #define DNN_BIAS_SHIFT_NUM_ITEM5_MASK 0xFF000000 //----------------------------------- #define CFG_DNN_SHIFT_NUM_W3_ADDR 0x94 #define DNN_SHIFT_NUM_ITEM6_OFFSET 0 #define DNN_SHIFT_NUM_ITEM6_MASK 0x000000FF #define DNN_BIAS_SHIFT_NUM_ITEM6_OFFSET 8 #define DNN_BIAS_SHIFT_NUM_ITEM6_MASK 0x0000FF00 #define DNN_SHIFT_NUM_ITEM7_OFFSET 16 #define DNN_SHIFT_NUM_ITEM7_MASK 0x00FF0000 #define DNN_BIAS_SHIFT_NUM_ITEM7_OFFSET 24 #define DNN_BIAS_SHIFT_NUM_ITEM7_MASK 0xFF000000 //----------------------------------- #define CFG_DNN_SHIFT_NUM_W4_ADDR 0x98 #define DNN_SHIFT_NUM_ITEM8_OFFSET 0 #define DNN_SHIFT_NUM_ITEM8_MASK 0x000000FF #define DNN_BIAS_SHIFT_NUM_ITEM8_OFFSET 8 #define DNN_BIAS_SHIFT_NUM_ITEM8_MASK 0x0000FF00 #define DNN_SHIFT_NUM_ITEM9_OFFSET 16 #define DNN_SHIFT_NUM_ITEM9_MASK 0x00FF0000 #define DNN_BIAS_SHIFT_NUM_ITEM9_OFFSET 24 #define DNN_BIAS_SHIFT_NUM_ITEM9_MASK 0xFF000000 //----------------------------------- #define CFG_DNN_SHIFT_NUM_W5_ADDR 0x9C #define DNN_SHIFT_NUM_ITEM10_OFFSET 0 #define DNN_SHIFT_NUM_ITEM10_MASK 0x000000FF #define DNN_BIAS_SHIFT_NUM_ITEM10_OFFSET 8 #define DNN_BIAS_SHIFT_NUM_ITEM10_MASK 0x0000FF00 #define DNN_SHIFT_NUM_ITEM11_OFFSET 16 #define DNN_SHIFT_NUM_ITEM11_MASK 0x00FF0000 #define DNN_BIAS_SHIFT_NUM_ITEM11_OFFSET 24 #define DNN_BIAS_SHIFT_NUM_ITEM11_MASK 0xFF000000 //----------------------------------- #define CFG_DNN_SHIFT_NUM_W6_ADDR 0xA0 #define DNN_SHIFT_NUM_ITEM12_OFFSET 0 #define DNN_SHIFT_NUM_ITEM12_MASK 0x000000FF #define DNN_BIAS_SHIFT_NUM_ITEM12_OFFSET 8 #define DNN_BIAS_SHIFT_NUM_ITEM12_MASK 0x0000FF00 #define DNN_SHIFT_NUM_ITEM13_OFFSET 16 #define DNN_SHIFT_NUM_ITEM13_MASK 0x00FF0000 #define DNN_BIAS_SHIFT_NUM_ITEM13_OFFSET 24 #define DNN_BIAS_SHIFT_NUM_ITEM13_MASK 0xFF000000 //----------------------------------- #define CFG_DNN_SHIFT_NUM_W7_ADDR 0xA4 #define DNN_SHIFT_NUM_ITEM14_OFFSET 0 #define DNN_SHIFT_NUM_ITEM14_MASK 0x000000FF #define DNN_BIAS_SHIFT_NUM_ITEM14_OFFSET 8 #define DNN_BIAS_SHIFT_NUM_ITEM14_MASK 0x0000FF00 #define DNN_SHIFT_NUM_ITEM15_OFFSET 16 #define DNN_SHIFT_NUM_ITEM15_MASK 0x00FF0000 #define DNN_BIAS_SHIFT_NUM_ITEM15_OFFSET 24 #define DNN_BIAS_SHIFT_NUM_ITEM15_MASK 0xFF000000 //----------------------------------- #define CFG_DNN_WI_PARAM_ADDR 0xA8 #define DNN_SOFTMAX_ALGRITHM_OFFSET 17 #define DNN_SOFTMAX_ALGRITHM_MASK 0x00020000 #define DNN_SOFTMAX_MINUS_EN_OFFSET 16 #define DNN_SOFTMAX_MINUS_EN_MASK 0x00010000 #define DNN_WI_8BIT_EN_OFFSET 0 #define DNN_WI_8BIT_EN_MASK 0x0000FFFF //----------------------------------- #define CFG_DNN_SOFMAX_PARAM_ADDR 0xAC #define DNN_MAX_CAL_EN_OFFSET 16 #define DNN_MAX_CAL_EN_MASK 0xFFFF0000 #define DNN_DEPTHWISE_EN_OFFSET 0 #define DNN_DEPTHWISE_EN_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_MAX_VALUE_WORD0_ADDR 0xb0 #define CNN_MAX_VALUE0_OFFSET 0 #define CNN_MAX_VALUE0_MASK 0x0000FFFF #define CNN_MAX_VALUE1_OFFSET 16 #define CNN_MAX_VALUE1_MASK 0xFFFF0000 //----------------------------------- #define CFG_CNN_MAX_VALUE_WORD1_ADDR 0xb4 #define CNN_MAX_VALUE2_OFFSET 0 #define CNN_MAX_VALUE2_MASK 0x0000FFFF #define CNN_MAX_VALUE3_OFFSET 16 #define CNN_MAX_VALUE3_MASK 0xFFFF0000 //----------------------------------- #define CFG_CNN_MAX_VALUE_WORD2_ADDR 0xb8 #define CNN_MAX_VALUE4_OFFSET 0 #define CNN_MAX_VALUE4_MASK 0x0000FFFF #define CNN_MAX_VALUE5_OFFSET 16 #define CNN_MAX_VALUE5_MASK 0xFFFF0000 //----------------------------------- #define CFG_CNN_MAX_VALUE_WORD3_ADDR 0xbC #define CNN_MAX_VALUE6_OFFSET 0 #define CNN_MAX_VALUE6_MASK 0x0000FFFF #define CNN_MAX_VALUE7_OFFSET 16 #define CNN_MAX_VALUE7_MASK 0xFFFF0000 //----------------------------------- #define CFG_CNN_MAX_VALUE_WORD4_ADDR 0xC0 #define CNN_MAX_VALUE8_OFFSET 0 #define CNN_MAX_VALUE8_MASK 0x0000FFFF #define CNN_MAX_VALUE9_OFFSET 16 #define CNN_MAX_VALUE9_MASK 0xFFFF0000 //----------------------------------- #define CFG_CNN_MAX_VALUE_WORD5_ADDR 0xC4 #define CNN_MAX_VALUE10_OFFSET 0 #define CNN_MAX_VALUE10_MASK 0x0000FFFF #define CNN_MAX_VALUE11_OFFSET 16 #define CNN_MAX_VALUE11_MASK 0xFFFF0000 //----------------------------------- #define CFG_CNN_MAX_VALUE_WORD6_ADDR 0xC8 #define CNN_MAX_VALUE12_OFFSET 0 #define CNN_MAX_VALUE12_MASK 0x0000FFFF #define CNN_MAX_VALUE13_OFFSET 16 #define CNN_MAX_VALUE13_MASK 0xFFFF0000 //----------------------------------- #define CFG_CNN_MAX_VALUE_WORD7_ADDR 0xCC #define CNN_MAX_VALUE14_OFFSET 0 #define CNN_MAX_VALUE14_MASK 0x0000FFFF #define CNN_MAX_VALUE15_OFFSET 16 #define CNN_MAX_VALUE15_MASK 0xFFFF0000 //----------------------------------- #define CFG_CNN_SOFTMAX_VALUE_WORD0_ADDR 0xd0 #define CNN_MAX_SX_VALUE0_OFFSET 0 #define CNN_MAX_SX_VALUE0_MASK 0x0000FFFF #define CNN_MAX_SX_VALUE1_OFFSET 16 #define CNN_MAX_SX_VALUE1_MASK 0xFFFF0000 //----------------------------------- #define CFG_CNN_SOFTMAX_VALUE_WORD1_ADDR 0xd4 #define CNN_SOFTMAX_VALUE2_OFFSET 0 #define CNN_SOFTMAX_VALUE2_MASK 0x0000FFFF #define CNN_SOFTMAX_VALUE3_OFFSET 16 #define CNN_SOFTMAX_VALUE3_MASK 0xFFFF0000 //----------------------------------- #define CFG_CNN_SOFTMAX_VALUE_WORD2_ADDR 0xd8 #define CNN_SOFTMAX_VALUE4_OFFSET 0 #define CNN_SOFTMAX_VALUE4_MASK 0x0000FFFF #define CNN_SOFTMAX_VALUE5_OFFSET 16 #define CNN_SOFTMAX_VALUE5_MASK 0xFFFF0000 //----------------------------------- #define CFG_CNN_SOFTMAX_VALUE_WORD3_ADDR 0xdc #define CNN_SOFTMAX_VALUE6_OFFSET 0 #define CNN_SOFTMAX_VALUE6_MASK 0x0000FFFF #define CNN_SOFTMAX_VALUE7_OFFSET 16 #define CNN_SOFTMAX_VALUE7_MASK 0xFFFF0000 //----------------------------------- #define CFG_CNN_SOFTMAX_VALUE_WORD4_ADDR 0xe0 #define CNN_SOFTMAX_VALUE8_OFFSET 0 #define CNN_SOFTMAX_VALUE8_MASK 0x0000FFFF #define CNN_SOFTMAX_VALUE9_OFFSET 16 #define CNN_SOFTMAX_VALUE9_MASK 0xFFFF0000 //----------------------------------- #define CFG_CNN_SOFTMAX_VALUE_WORD5_ADDR 0xe4 #define CNN_SOFTMAX_VALUE10_OFFSET 0 #define CNN_SOFTMAX_VALUE10_MASK 0x0000FFFF #define CNN_SOFTMAX_VALUE11_OFFSET 16 #define CNN_SOFTMAX_VALUE11_MASK 0xFFFF0000 //----------------------------------- #define CFG_CNN_SOFTMAX_VALUE_WORD6_ADDR 0xe8 #define CNN_SOFTMAX_VALUE12_OFFSET 0 #define CNN_SOFTMAX_VALUE12_MASK 0x0000FFFF #define CNN_SOFTMAX_VALUE13_OFFSET 16 #define CNN_SOFTMAX_VALUE13_MASK 0xFFFF0000 //----------------------------------- #define CFG_CNN_SOFTMAX_VALUE_WORD7_ADDR 0xec #define CNN_SOFTMAX_VALUE14_OFFSET 0 #define CNN_SOFTMAX_VALUE14_MASK 0x0000FFFF #define CNN_SOFTMAX_VALUE15_OFFSET 16 #define CNN_SOFTMAX_VALUE15_MASK 0xFFFF0000 //----------------------------------- #define CFG_CNN_DMA_NEXT_CFG_START_ADDRESS_ADDR 0x1000 #define DMA_NEXT_CFG_START_ADDRESS_OFFSET 5 #define DMA_NEXT_CFG_START_ADDRESS_MASK 0xFFFFFFE0 //----------------------------------- #define CFG_CNN_DMA_EXT_FI_START_ADDRESS_ADDR 0x1004 #define DMA_EXT_FI_START_ADDRESS_OFFSET 5 #define DMA_EXT_FI_START_ADDRESS_MASK 0xFFFFFFE0 //----------------------------------- #define CFG_CNN_DMA_EXT_WI_START_ADDRESS_ADDR 0x1008 #define DMA_EXT_WI_START_ADDRESS_OFFSET 5 #define DMA_EXT_WI_START_ADDRESS_MASK 0xFFFFFFE0 //----------------------------------- #define CFG_CNN_DMA_EXT_FO_START_ADDRESS_ADDR 0x100C #define DMA_EXT_FO_START_ADDRESS_OFFSET 5 #define DMA_EXT_FO_START_ADDRESS_MASK 0xFFFFFFE0 //----------------------------------- #define CFG_CNN_FI_SIZE_ADDR 0x1010 #define CNN_WI_OFFSET 16 #define CNN_WI_MASK 0xFFFF0000 #define CNN_HI_OFFSET 0 #define CNN_HI_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_FI_NUM_ADDR 0x1014 #define CNN_FI_NUM_OFFSET 16 #define CNN_FI_NUM_MASK 0xFFFF0000 #define CNN_C_OFFSET 0 #define CNN_C_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_PARAM0_ADDR 0x1018 #define CNN_KY_OFFSET 28 #define CNN_KY_MASK 0xF0000000 #define CNN_KX_OFFSET 24 #define CNN_KX_MASK 0x0F000000 #define CNN_D_OFFSET 20 #define CNN_D_MASK 0x00F00000 #define CNN_S_OFFSET 16 #define CNN_S_MASK 0x000F0000 #define CNN_G_OFFSET 0 #define CNN_G_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_PARAM1_ADDR 0x101C #define CNN_FO_HANG_DMA_REQ_EN_OFFSET 25 #define CNN_FO_HANG_DMA_REQ_EN_MASK 0x02000000 #define CNN_FI_DMA_INTERNAL_MODE_OFFSET 24 #define CNN_FI_DMA_INTERNAL_MODE_MASK 0x01000000 #define CNN_FO_DMA_INTERNAL_MODE_OFFSET 23 #define CNN_FO_DMA_INTERNAL_MODE_MASK 0x00800000 #define CNN_FO_DMA_HANG_FSM_EN_OFFSET 22 #define CNN_FO_DMA_HANG_FSM_EN_MASK 0x00400000 #define CNN_SOFTMAX_ALGRITHM_OFFSET 21 #define CNN_SOFTMAX_ALGRITHM_MASK 0x00200000 #define CNN_MAX_CAL_EN_OFFSET 20 #define CNN_MAX_CAL_EN_MASK 0x00100000 #define CNN_LL_START_TYPES_OFFSET 12 #define CNN_LL_START_TYPES_MASK 0x000FF000 #define CNN_LL_START_TYPES_SEL_OFFSET 11 #define CNN_LL_START_TYPES_SEL_MASK 0x00000800 #define CNN_3D_DEPTH_CAL_ONLY_OFFSET 10 #define CNN_3D_DEPTH_CAL_ONLY_MASK 0x00000400 #define CNN_PRELU_SHIFT_NUM_OFFSET 8 #define CNN_PRELU_SHIFT_NUM_MASK 0x00000300 #define CNN_3D_DEPTH_CAL_EN_OFFSET 7 #define CNN_3D_DEPTH_CAL_EN_MASK 0x00000080 #define CNN_8BIT_WEIGHT_EN_OFFSET 6 #define CNN_8BIT_WEIGHT_EN_MASK 0x00000040 #define CNN_NONLINEARITY_ALGRITH_OFFSET 3 #define CNN_NONLINEARITY_ALGRITH_MASK 0x00000038 #define CNN_SOFTMAX_MINUS_EN_OFFSET 2 #define CNN_SOFTMAX_MINUS_EN_MASK 0x00000004 #define CNN_SOFMAX_EN_OFFSET 1 #define CNN_SOFMAX_EN_MASK 0x00000002 #define CNN_BIAS_EN_OFFSET 0 #define CNN_BIAS_EN_MASK 0x00000001 //----------------------------------- #define CFG_CNN_POOLING_PARAM_ADDR 0x1020 #define CNN_SHIFT_NUM_ACC_OFFSET 24 #define CNN_SHIFT_NUM_ACC_MASK 0xFF000000 #define CNN_SHIFT_NUM_BIAS_OFFSET 16 #define CNN_SHIFT_NUM_BIAS_MASK 0x00FF0000 #define CNN_POOLING_ALGRITH_OFFSET 8 #define CNN_POOLING_ALGRITH_MASK 0x00000100 //----------------------------------- #define CFG_CNN_MAC_MASK_PARAM_ADDR 0x1024 #define CNN_MAC_ROW_Y_MASK_OFFSET 16 #define CNN_MAC_ROW_Y_MASK_MASK 0xFFFF0000 #define CNN_MAC_ROW_X_MASK_OFFSET 0 #define CNN_MAC_ROW_X_MASK_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_MAC_PARAM_ADDR 0x1028 #define CNN_HUFFMAN_ZERO_VALUE_OFFSET 16 #define CNN_HUFFMAN_ZERO_VALUE_MASK 0xFFFF0000 #define CNN_HUFFMAN_EN_OFFSET 3 #define CNN_HUFFMAN_EN_MASK 0x00000008 #define CNN_MAC_TYPE_OFFSET 2 #define CNN_MAC_TYPE_MASK 0x00000004 #define CNN_MAC8X8_OP1_SIGN_OFFSET 1 #define CNN_MAC8X8_OP1_SIGN_MASK 0x00000002 #define CNN_MAC8X8_OP2_SIGN_OFFSET 0 #define CNN_MAC8X8_OP2_SIGN_MASK 0x00000001 //----------------------------------- #define CFG_CNN_EXP_PARAM_ADDR 0x102C #define CNN_BIAS_SW_EN_OFFSET 17 #define CNN_BIAS_SW_EN_MASK 0x00020000 #define CNN_WEIGHT_SW_EN_OFFSET 16 #define CNN_WEIGHT_SW_EN_MASK 0x00010000 #define CNN_WEIGHT_SW_OFFSET 0 #define CNN_WEIGHT_SW_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_INT_EN_ADDR 0x1030 #define CNN_ALL_DONE_RAW_INT_EN_OFFSET 31 #define CNN_ALL_DONE_RAW_INT_EN_MASK 0x80000000 #define CNN_LL_RAW_INT_EN_OFFSET 30 #define CNN_LL_RAW_INT_EN_MASK 0x40000000 #define CNN_3D_DONE_RAW_INT_EN_OFFSET 29 #define CNN_3D_DONE_RAW_INT_EN_MASK 0x20000000 #define CNN_2D_DONE_RAW_INT_EN_OFFSET 28 #define CNN_2D_DONE_RAW_INT_EN_MASK 0x10000000 #define CNN_1D_DONE_RAW_INT_EN_OFFSET 27 #define CNN_1D_DONE_RAW_INT_EN_MASK 0x08000000 #define CNN_ELEM_DONE_RAW_INT_EN_OFFSET 26 #define CNN_ELEM_DONE_RAW_INT_EN_MASK 0x04000000 #define CNN_3D_START_RAW_INT_EN_OFFSET 25 #define CNN_3D_START_RAW_INT_EN_MASK 0x02000000 #define CNN_2D_START_RAW_INT_EN_OFFSET 24 #define CNN_2D_START_RAW_INT_EN_MASK 0x01000000 #define CNN_FSM_FI_DMA_REQ_RAW_INT_EN_OFFSET 23 #define CNN_FSM_FI_DMA_REQ_RAW_INT_EN_MASK 0x00800000 #define CNN_FSM_WI_DMA_REQ_RAW_INT_EN_OFFSET 22 #define CNN_FSM_WI_DMA_REQ_RAW_INT_EN_MASK 0x00400000 #define CNN_GROUP_DONE_RAW_INT_EN_OFFSET 21 #define CNN_GROUP_DONE_RAW_INT_EN_MASK 0x00200000 #define CNN_LL_NUM_DONE_RAW_INT_EN_OFFSET 20 #define CNN_LL_NUM_DONE_RAW_INT_EN_MASK 0x00100000 #define CNN_DMA_CFG_DONE_RAW_INT_EN_OFFSET 19 #define CNN_DMA_CFG_DONE_RAW_INT_EN_MASK 0x00080000 #define CNN_DMA_FO_INT_DONE_CLR_OFFSET 18 #define CNN_DMA_FO_INT_DONE_CLR_MASK 0x00040000 #define CNN_DMA_FI_INT_DONE_CLR_OFFSET 17 #define CNN_DMA_FI_INT_DONE_CLR_MASK 0x00020000 #define CNN_DMA_WI_INT_DONE_CLR_OFFSET 16 #define CNN_DMA_WI_INT_DONE_CLR_MASK 0x00010000 #define CNN_GROUP_CNT7_DONE_RAW_INT_EN_OFFSET 15 #define CNN_GROUP_CNT7_DONE_RAW_INT_EN_MASK 0x00008000 #define CNN_GROUP_CNT6_DONE_RAW_INT_EN_OFFSET 14 #define CNN_GROUP_CNT6_DONE_RAW_INT_EN_MASK 0x00004000 #define CNN_GROUP_CNT5_DONE_RAW_INT_EN_OFFSET 13 #define CNN_GROUP_CNT5_DONE_RAW_INT_EN_MASK 0x00002000 #define CNN_GROUP_CNT4_DONE_RAW_INT_EN_OFFSET 12 #define CNN_GROUP_CNT4_DONE_RAW_INT_EN_MASK 0x00001000 #define CNN_GROUP_CNT3_DONE_RAW_INT_EN_OFFSET 11 #define CNN_GROUP_CNT3_DONE_RAW_INT_EN_MASK 0x00000800 #define CNN_GROUP_CNT2_DONE_RAW_INT_EN_OFFSET 10 #define CNN_GROUP_CNT2_DONE_RAW_INT_EN_MASK 0x00000400 #define CNN_GROUP_CNT1_DONE_RAW_INT_EN_OFFSET 9 #define CNN_GROUP_CNT1_DONE_RAW_INT_EN_MASK 0x00000200 #define CNN_GROUP_CNT0_DONE_RAW_INT_EN_OFFSET 8 #define CNN_GROUP_CNT0_DONE_RAW_INT_EN_MASK 0x00000100 #define CNN_LL_CNT7_DONE_RAW_INT_EN_OFFSET 7 #define CNN_LL_CNT7_DONE_RAW_INT_EN_MASK 0x00000080 #define CNN_LL_CNT6_DONE_RAW_INT_EN_OFFSET 6 #define CNN_LL_CNT6_DONE_RAW_INT_EN_MASK 0x00000040 #define CNN_LL_CNT5_DONE_RAW_INT_EN_OFFSET 5 #define CNN_LL_CNT5_DONE_RAW_INT_EN_MASK 0x00000020 #define CNN_LL_CNT4_DONE_RAW_INT_EN_OFFSET 4 #define CNN_LL_CNT4_DONE_RAW_INT_EN_MASK 0x00000010 #define CNN_LL_CNT3_DONE_RAW_INT_EN_OFFSET 3 #define CNN_LL_CNT3_DONE_RAW_INT_EN_MASK 0x00000008 #define CNN_LL_CNT2_DONE_RAW_INT_EN_OFFSET 2 #define CNN_LL_CNT2_DONE_RAW_INT_EN_MASK 0x00000004 #define CNN_LL_CNT1_DONE_RAW_INT_EN_OFFSET 1 #define CNN_LL_CNT1_DONE_RAW_INT_EN_MASK 0x00000002 #define CNN_LL_CNT0_DONE_RAW_INT_EN_OFFSET 0 #define CNN_LL_CNT0_DONE_RAW_INT_EN_MASK 0x00000001 //----------------------------------- #define CFG_CNN_INT_HALT_EN_ADDR 0x1034 #define CNN_ALL_DONE_RAW_INT_HALT_EN_OFFSET 31 #define CNN_ALL_DONE_RAW_INT_HALT_EN_MASK 0x80000000 #define CNN_LL_RAW_INT_HALT_EN_OFFSET 30 #define CNN_LL_RAW_INT_HALT_EN_MASK 0x40000000 #define CNN_3D_DONE_RAW_INT_HALT_EN_OFFSET 29 #define CNN_3D_DONE_RAW_INT_HALT_EN_MASK 0x20000000 #define CNN_2D_DONE_RAW_INT_HALT_EN_OFFSET 28 #define CNN_2D_DONE_RAW_INT_HALT_EN_MASK 0x10000000 #define CNN_1D_DONE_RAW_INT_HALT_EN_OFFSET 27 #define CNN_1D_DONE_RAW_INT_HALT_EN_MASK 0x08000000 #define CNN_ELEM_DONE_RAW_INT_HALT_EN_OFFSET 26 #define CNN_ELEM_DONE_RAW_INT_HALT_EN_MASK 0x04000000 #define CNN_3D_START_RAW_INT_HALT_EN_OFFSET 25 #define CNN_3D_START_RAW_INT_HALT_EN_MASK 0x02000000 #define CNN_2D_START_RAW_INT_HALT_EN_OFFSET 24 #define CNN_2D_START_RAW_INT_HALT_EN_MASK 0x01000000 #define CNN_FSM_FI_DMA_REQ_RAW_INT_HALT_EN_OFFSET 23 #define CNN_FSM_FI_DMA_REQ_RAW_INT_HALT_EN_MASK 0x00800000 #define CNN_FSM_WI_DMA_REQ_RAW_INT_HALT_EN_OFFSET 22 #define CNN_FSM_WI_DMA_REQ_RAW_INT_HALT_EN_MASK 0x00400000 #define CNN_GROUP_DONE_RAW_INT_HALT_EN_OFFSET 21 #define CNN_GROUP_DONE_RAW_INT_HALT_EN_MASK 0x00200000 #define CNN_LL_NUM_DONE_RAW_INT_HALT_EN_OFFSET 20 #define CNN_LL_NUM_DONE_RAW_INT_HALT_EN_MASK 0x00100000 #define CNN_DMA_CFG_DONE_RAW_INT_HALT_EN_OFFSET 19 #define CNN_DMA_CFG_DONE_RAW_INT_HALT_EN_MASK 0x00080000 #define CNN_DMA_FO_INT_DONE_CLR_OFFSET 18 #define CNN_DMA_FO_INT_DONE_CLR_MASK 0x00040000 #define CNN_DMA_FI_INT_DONE_CLR_OFFSET 17 #define CNN_DMA_FI_INT_DONE_CLR_MASK 0x00020000 #define CNN_DMA_WI_INT_DONE_CLR_OFFSET 16 #define CNN_DMA_WI_INT_DONE_CLR_MASK 0x00010000 #define CNN_GROUP_CNT7_DONE_RAW_INT_HALT_EN_OFFSET 15 #define CNN_GROUP_CNT7_DONE_RAW_INT_HALT_EN_MASK 0x00008000 #define CNN_GROUP_CNT6_DONE_RAW_INT_HALT_EN_OFFSET 14 #define CNN_GROUP_CNT6_DONE_RAW_INT_HALT_EN_MASK 0x00004000 #define CNN_GROUP_CNT5_DONE_RAW_INT_HALT_EN_OFFSET 13 #define CNN_GROUP_CNT5_DONE_RAW_INT_HALT_EN_MASK 0x00002000 #define CNN_GROUP_CNT4_DONE_RAW_INT_HALT_EN_OFFSET 12 #define CNN_GROUP_CNT4_DONE_RAW_INT_HALT_EN_MASK 0x00001000 #define CNN_GROUP_CNT3_DONE_RAW_INT_HALT_EN_OFFSET 11 #define CNN_GROUP_CNT3_DONE_RAW_INT_HALT_EN_MASK 0x00000800 #define CNN_GROUP_CNT2_DONE_RAW_INT_HALT_EN_OFFSET 10 #define CNN_GROUP_CNT2_DONE_RAW_INT_HALT_EN_MASK 0x00000400 #define CNN_GROUP_CNT1_DONE_RAW_INT_HALT_EN_OFFSET 9 #define CNN_GROUP_CNT1_DONE_RAW_INT_HALT_EN_MASK 0x00000200 #define CNN_GROUP_CNT0_DONE_RAW_INT_HALT_EN_OFFSET 8 #define CNN_GROUP_CNT0_DONE_RAW_INT_HALT_EN_MASK 0x00000100 #define CNN_LL_CNT7_DONE_RAW_INT_HALT_EN_OFFSET 7 #define CNN_LL_CNT7_DONE_RAW_INT_HALT_EN_MASK 0x00000080 #define CNN_LL_CNT6_DONE_RAW_INT_HALT_EN_OFFSET 6 #define CNN_LL_CNT6_DONE_RAW_INT_HALT_EN_MASK 0x00000040 #define CNN_LL_CNT5_DONE_RAW_INT_HALT_EN_OFFSET 5 #define CNN_LL_CNT5_DONE_RAW_INT_HALT_EN_MASK 0x00000020 #define CNN_LL_CNT4_DONE_RAW_INT_HALT_EN_OFFSET 4 #define CNN_LL_CNT4_DONE_RAW_INT_HALT_EN_MASK 0x00000010 #define CNN_LL_CNT3_DONE_RAW_INT_HALT_EN_OFFSET 3 #define CNN_LL_CNT3_DONE_RAW_INT_HALT_EN_MASK 0x00000008 #define CNN_LL_CNT2_DONE_RAW_INT_HALT_EN_OFFSET 2 #define CNN_LL_CNT2_DONE_RAW_INT_HALT_EN_MASK 0x00000004 #define CNN_LL_CNT1_DONE_RAW_INT_HALT_EN_OFFSET 1 #define CNN_LL_CNT1_DONE_RAW_INT_HALT_EN_MASK 0x00000002 #define CNN_LL_CNT0_DONE_RAW_INT_HALT_EN_OFFSET 0 #define CNN_LL_CNT0_DONE_RAW_INT_HALT_EN_MASK 0x00000001 //----------------------------------- #define CFG_CNN_FO_RANGE_ADDR 0x1038 #define CNN_FO_Y_RANGE_OFFSET 16 #define CNN_FO_Y_RANGE_MASK 0xFFFF0000 #define CNN_FO_X_RANGE_OFFSET 0 #define CNN_FO_X_RANGE_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_DMA_CFG_ADDR 0x103C #define CNN_NXT_PADDING_LEFT_OFFSET 28 #define CNN_NXT_PADDING_LEFT_MASK 0xF0000000 #define CNN_NXT_PADDING_DOWN_OFFSET 24 #define CNN_NXT_PADDING_DOWN_MASK 0x0F000000 #define CNN_NXT_PADDING_UP_OFFSET 20 #define CNN_NXT_PADDING_UP_MASK 0x00F00000 #define CNN_FI_OPTIMIZE_MODE_OFFSET 19 #define CNN_FI_OPTIMIZE_MODE_MASK 0x00080000 #define FO_DUMP_MODE_OFFSET 18 #define FO_DUMP_MODE_MASK 0x00040000 #define CNN_NXT_FI_PADDING_TYPE_OFFSET 17 #define CNN_NXT_FI_PADDING_TYPE_MASK 0x00020000 #define CNN_FO_OPTIMIZE_MODE_OFFSET 16 #define CNN_FO_OPTIMIZE_MODE_MASK 0x00010000 #define CNN_DMA_BUF_BURST_TYPE_OFFSET 12 #define CNN_DMA_BUF_BURST_TYPE_MASK 0x0000F000 #define FILTER_QUAT_MODE_OFFSET 11 #define FILTER_QUAT_MODE_MASK 0x00000800 #define MEM_MAP_OFFSET 4 #define MEM_MAP_MASK 0x000007F0 #define INIT_WI_DMA_BYPASS_OFFSET 3 #define INIT_WI_DMA_BYPASS_MASK 0x00000008 #define INIT_FI_DMA_BYPASS_OFFSET 2 #define INIT_FI_DMA_BYPASS_MASK 0x00000004 #define DMA_HALF_DUMP_FO_EN_OFFSET 1 #define DMA_HALF_DUMP_FO_EN_MASK 0x00000002 #define DMA_DUMP_FO_EN_OFFSET 0 #define DMA_DUMP_FO_EN_MASK 0x00000001 //----------------------------------- #define CFG_CNN_DERIVE_PARAM0_ADDR 0x1040 #define CNN_DMA_SEQ_ROW_NUM_FI_OFFSET 16 #define CNN_DMA_SEQ_ROW_NUM_FI_MASK 0xFFFF0000 #define CNN_DMA_INIT_ROW_NUM_FI_OFFSET 0 #define CNN_DMA_INIT_ROW_NUM_FI_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM1_ADDR 0x1044 #define CNN_WI_RAM_BT_ALL_FILTER_OFFSET 20 #define CNN_WI_RAM_BT_ALL_FILTER_MASK 0x00100000 #define CNN_WI_RAM_BT_16_FILTER_OFFSET 19 #define CNN_WI_RAM_BT_16_FILTER_MASK 0x00080000 #define CNN_WI_RAM_BT_8_FILTER_OFFSET 18 #define CNN_WI_RAM_BT_8_FILTER_MASK 0x00040000 #define CNN_WI_RAM_BT_4_FILTER_OFFSET 17 #define CNN_WI_RAM_BT_4_FILTER_MASK 0x00020000 #define CNN_WI_RAM_BT_1_FILTER_OFFSET 16 #define CNN_WI_RAM_BT_1_FILTER_MASK 0x00010000 #define CNN_FI_RAM_BT_K_ROW_FI_OFFSET 15 #define CNN_FI_RAM_BT_K_ROW_FI_MASK 0x00008000 #define CNN_FI_RAM_BT_ALL_FI_OFFSET 14 #define CNN_FI_RAM_BT_ALL_FI_MASK 0x00004000 #define CNN_DXK_D_Y_OFFSET 7 #define CNN_DXK_D_Y_MASK 0x00003F80 #define CNN_DXK_D_X_OFFSET 0 #define CNN_DXK_D_X_MASK 0x0000007F //----------------------------------- #define CFG_CNN_DERIVE_PARAM2_ADDR 0x1048 #define CNN_FI_SXCXW_DIV32_OFFSET 16 #define CNN_FI_SXCXW_DIV32_MASK 0xFFFF0000 #define CNN_CXW_DI32_OFFSET 0 #define CNN_CXW_DI32_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM3_ADDR 0x104C #define CNN_FI_WI_DIV_16_OFFSET 0 #define CNN_FI_WI_DIV_16_MASK 0x0000FFFF #define CNN_FI_WI_DIV_16S_OFFSET 0 #define CNN_FI_WI_DIV_16S_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM4_ADDR 0x1050 #define CNN_HIXWI_DIV32_OFFSET 0 #define CNN_HIXWI_DIV32_MASK 0x000FFFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM5_ADDR 0x1054 #define CNN_PADDING_BITS_Y_DOWN_OFFSET 28 #define CNN_PADDING_BITS_Y_DOWN_MASK 0xF0000000 #define CNN_PADDING_BITS_Y_UP_OFFSET 24 #define CNN_PADDING_BITS_Y_UP_MASK 0x0F000000 #define CNN_PADDING_BITS_X_OFFSET 20 #define CNN_PADDING_BITS_X_MASK 0x00F00000 #define CNN_KXKXC_OFFSET 0 #define CNN_KXKXC_MASK 0x000FFFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM6_ADDR 0x1058 #define CNN_ELEM_CAL_DLY_OFFSET 16 #define CNN_ELEM_CAL_DLY_MASK 0x00FF0000 #define CNN_FI_HI_DIV_S_OFFSET 0 #define CNN_FI_HI_DIV_S_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM7_ADDR 0x105C #define CNN_FO_CO_DISTANCE_OFFSET 0 #define CNN_FO_CO_DISTANCE_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM8_ADDR 0x1060 #define CNN_16FILTER_DISTANCE_OFFSET 0 #define CNN_16FILTER_DISTANCE_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM9_ADDR 0x1064 #define CNN_GROUP_FI_DISTANCE_OFFSET 0 #define CNN_GROUP_FI_DISTANCE_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM10_ADDR 0x1068 #define CNN_FI_PADDING_WI_DIV_16_OFFSET 16 #define CNN_FI_PADDING_WI_DIV_16_MASK 0xFFFF0000 #define CNN_FI_PADDING_WI_DIV_16S_OFFSET 0 #define CNN_FI_PADDING_WI_DIV_16S_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM11_ADDR 0x106C #define CNN_KXKXCXFI_DIV16_OFFSET 0 #define CNN_KXKXCXFI_DIV16_MASK 0x000FFFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM12_ADDR 0x1070 #define CNN_GROUP_FO_DISTANCE_OFFSET 0 #define CNN_GROUP_FO_DISTANCE_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM13_ADDR 0x1074 #define CNN_1_DIV_K2_OFFSET 16 #define CNN_1_DIV_K2_MASK 0xFFFF0000 #define CNN_1_DIV_K1_OFFSET 0 #define CNN_1_DIV_K1_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM14_ADDR 0x1078 #define CNN_1_DIV_K4_OFFSET 16 #define CNN_1_DIV_K4_MASK 0xFFFF0000 #define CNN_1_DIV_K3_OFFSET 0 #define CNN_1_DIV_K3_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM15_ADDR 0x107C #define CNN_1_DIV_K6_OFFSET 16 #define CNN_1_DIV_K6_MASK 0xFFFF0000 #define CNN_1_DIV_K5_OFFSET 0 #define CNN_1_DIV_K5_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM16_ADDR 0x1080 #define CNN_1_DIV_K8_OFFSET 16 #define CNN_1_DIV_K8_MASK 0xFFFF0000 #define CNN_1_DIV_K7_OFFSET 0 #define CNN_1_DIV_K7_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM17_ADDR 0x1084 #define CNN_FO_MINUS_VALUE_OFFSET 16 #define CNN_FO_MINUS_VALUE_MASK 0xFFFF0000 #define CNN_1_DIV_K9_OFFSET 0 #define CNN_1_DIV_K9_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM18_ADDR 0x1088 #define CNN_FI_MINUS_VALUE_OFFSET 16 #define CNN_FI_MINUS_VALUE_MASK 0xFFFF0000 #define CNN_WI_MINUS_VALUE_OFFSET 0 #define CNN_WI_MINUS_VALUE_MASK 0x0000FFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM19_ADDR 0x108C #define CNN_IMEM_FO_GROUP_DISTANCE_OFFSET 0 #define CNN_IMEM_FO_GROUP_DISTANCE_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CNN_DERIVE_PARAM20_ADDR 0x1090 #define CNN_FILTER_FO_SIZE_OFFSET 0 #define CNN_FILTER_FO_SIZE_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CNN_FUNC_CLK_DISABLE_ADDR 0x1094 #define CNN_FUNC_CLK_DISABLE_OFFSET 0 #define CNN_FUNC_CLK_DISABLE_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CNN_FI_HI_BOUNDARY_MASK_ADDR 0x1098 #define CNN_FI_HI_BOUNDARY_MASK_OFFSET 0 #define CNN_FI_HI_BOUNDARY_MASK_MASK 0xFFFFFFFF //HW module read/write macro #define CNN_READ_REG(addr) SOC_READ_REG(CNN_BASEADDR + addr) #define CNN_WRITE_REG(addr,value) SOC_WRITE_REG(CNN_BASEADDR + addr,value)