//----------------------------------- #define CFG_DDR_REG_RVER_ADDR 0x0 #define DDR_RF_VER_OFFSET 0 #define DDR_RF_VER_MASK 0x0000FFFF //----------------------------------- #define CFG_DDR_RST_CFG_ADDR 0x4 #define SAMPLE_REG_SOFT_RST_OFFSET 7 #define SAMPLE_REG_SOFT_RST_MASK 0x00000080 #define RXTX_RAM_SOFT_RST_OFFSET 6 #define RXTX_RAM_SOFT_RST_MASK 0x00000040 #define DL_SOFT_RST_OFFSET 5 #define DL_SOFT_RST_MASK 0x00000020 #define CHIP_PWR_UP_OFFSET 4 #define CHIP_PWR_UP_MASK 0x00000010 #define ARBIT_INIT_OFFSET 3 #define ARBIT_INIT_MASK 0x00000008 #define SOFT_FSM_RST_OFFSET 2 #define SOFT_FSM_RST_MASK 0x00000004 #define DL0_SOFT_RST_OFFSET 1 #define DL0_SOFT_RST_MASK 0x00000002 #define DL12_SOFT_RST_OFFSET 0 #define DL12_SOFT_RST_MASK 0x00000001 //----------------------------------- #define CFG_DDR_PROPERTY_CFG_ADDR 0x8 #define CS3_SW_SEL_OFFSET 18 #define CS3_SW_SEL_MASK 0x00040000 #define CS2_SW_SEL_OFFSET 17 #define CS2_SW_SEL_MASK 0x00020000 #define CS1_SW_SEL_OFFSET 16 #define CS1_SW_SEL_MASK 0x00010000 #define CS0_SW_SEL_OFFSET 15 #define CS0_SW_SEL_MASK 0x00008000 #define DDR_CP1_LDO_SEL1P8_B_OFFSET 14 #define DDR_CP1_LDO_SEL1P8_B_MASK 0x00004000 #define DDR_CP0_LDO_SEL1P8_B_OFFSET 13 #define DDR_CP0_LDO_SEL1P8_B_MASK 0x00002000 #define PAD_CLK_FRC_ON_OFFSET 12 #define PAD_CLK_FRC_ON_MASK 0x00001000 #define CS3_FRC_ON_OFFSET 11 #define CS3_FRC_ON_MASK 0x00000800 #define CS2_FRC_ON_OFFSET 10 #define CS2_FRC_ON_MASK 0x00000400 #define CS1_FRC_ON_OFFSET 9 #define CS1_FRC_ON_MASK 0x00000200 #define CS0_FRC_ON_OFFSET 8 #define CS0_FRC_ON_MASK 0x00000100 #define CS_SIZE_OFFSET 4 #define CS_SIZE_MASK 0x000000F0 #define DEV_CS_INTG_OFFSET 2 #define DEV_CS_INTG_MASK 0x00000004 #define DEV_X8_X16_MODE_OFFSET 1 #define DEV_X8_X16_MODE_MASK 0x00000002 #define DQS_DM_SEPARATE_OFFSET 0 #define DQS_DM_SEPARATE_MASK 0x00000001 //----------------------------------- #define CFG_DDR_GEN_CMD_ST_ADDR 0xC #define GEN_CMD_DONE_OFFSET 12 #define GEN_CMD_DONE_MASK 0x00001000 #define CMD_ST_TOTAL_DLY_OFFSET 4 #define CMD_ST_TOTAL_DLY_MASK 0x000007F0 #define GEN_CMD_EARLY_NUM_OFFSET 0 #define GEN_CMD_EARLY_NUM_MASK 0x0000000F //----------------------------------- #define CFG_DDR_CMD_DLY_CFG_ADDR 0x10 #define DEV_RD_LATENCY_OFFSET 20 #define DEV_RD_LATENCY_MASK 0x00F00000 #define DEV_WR_LATENCY_OFFSET 16 #define DEV_WR_LATENCY_MASK 0x000F0000 #define CMD_INST_DUMMY_DLY_OFFSET 12 #define CMD_INST_DUMMY_DLY_MASK 0x0000F000 #define CMD_A2_DUMMY_DLY_OFFSET 8 #define CMD_A2_DUMMY_DLY_MASK 0x00000F00 #define CMD_A1_DUMMY_DLY_OFFSET 4 #define CMD_A1_DUMMY_DLY_MASK 0x000000F0 #define CMD_A0_DUMMY_DLY_OFFSET 0 #define CMD_A0_DUMMY_DLY_MASK 0x0000000F //----------------------------------- #define CFG_DDR_PAGE_BOUNDARY_ADDR 0x14 #define DDR_PAGE_BOUNDARY_OFFSET 0 #define DDR_PAGE_BOUNDARY_MASK 0x0000000F //----------------------------------- #define CFG_DDR_SPEC_REG_CFG_ADDR 0x18 #define DEV_MD1_ADDR_OFFSET 24 #define DEV_MD1_ADDR_MASK 0xFF000000 #define CALIB_MD1_VAL_OFFSET 16 #define CALIB_MD1_VAL_MASK 0x00FF0000 #define DEV_MD0_ADDR_OFFSET 8 #define DEV_MD0_ADDR_MASK 0x0000FF00 #define CALIB_MD0_VAL_OFFSET 0 #define CALIB_MD0_VAL_MASK 0x000000FF //----------------------------------- #define CFG_DDR_SOFT_CMD_CFG0_ADDR 0x1C #define DEV_OPERATION_SW_OFFSET 8 #define DEV_OPERATION_SW_MASK 0x00000100 #define DEV_CMD_SW_OFFSET 0 #define DEV_CMD_SW_MASK 0x000000FF //----------------------------------- #define CFG_DDR_SOFT_CMD_CFG1_ADDR 0x20 #define DEV_ADDR_SW_OFFSET 0 #define DEV_ADDR_SW_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DDR_DL_TRAINING_CFG0_ADDR 0x24 #define TRAINING_FORCE_DONE_OFFSET 14 #define TRAINING_FORCE_DONE_MASK 0x00004000 #define TRAINING_AUTO_EN_OFFSET 13 #define TRAINING_AUTO_EN_MASK 0x00002000 #define DL12_TRAINING_FORCE_START_OFFSET 12 #define DL12_TRAINING_FORCE_START_MASK 0x00001000 #define DL12_CNT_VALUE_SW_OFFSET 4 #define DL12_CNT_VALUE_SW_MASK 0x00000FF0 #define DL12_CFG_DLY_OFFSET 0 #define DL12_CFG_DLY_MASK 0x0000000F //----------------------------------- #define CFG_DDR_DL_DEMO_TRAINING_CFG0_ADDR 0x28 #define DL0_TRAINING_FORCE_START_OFFSET 19 #define DL0_TRAINING_FORCE_START_MASK 0x00080000 #define DL0_MONITIOR_EB_OFFSET 18 #define DL0_MONITIOR_EB_MASK 0x00040000 #define DL0_MONITIOR_RESTART_OFFSET 17 #define DL0_MONITIOR_RESTART_MASK 0x00020000 #define DL0_TRAINING_AUTO_EN_OFFSET 16 #define DL0_TRAINING_AUTO_EN_MASK 0x00010000 #define DL0_FETCH_RESULT_DLY_OFFSET 8 #define DL0_FETCH_RESULT_DLY_MASK 0x0000FF00 #define DL0_MONITIOR_DLY_OFFSET 0 #define DL0_MONITIOR_DLY_MASK 0x000000FF //----------------------------------- #define CFG_DDR_TX_DL_TRAINING_CFG_ADDR 0x2C #define TX_DL_EB_OFFSET 8 #define TX_DL_EB_MASK 0x00000100 #define TX_DL_CFG_DATA_OFFSET 0 #define TX_DL_CFG_DATA_MASK 0x000000FF //----------------------------------- #define CFG_DDR_DELAYLINE0_CFG_ADDR 0x34 #define DL0_SAMPLE_VALUE_OFFSET 24 #define DL0_SAMPLE_VALUE_MASK 0x03000000 #define DL0_CNT_VALUE_OFFSET 16 #define DL0_CNT_VALUE_MASK 0x00FF0000 #define DL0_CNT_ADD_SUB_SEL_OFFSET 15 #define DL0_CNT_ADD_SUB_SEL_MASK 0x00008000 #define DL0_SW_CNT_SOFT_RST_OFFSET 14 #define DL0_SW_CNT_SOFT_RST_MASK 0x00004000 #define DL0_SW_CLK_OUT_FRC_ON_OFFSET 13 #define DL0_SW_CLK_OUT_FRC_ON_MASK 0x00002000 #define DL0_SW_CLK_IN_FRC_ON_OFFSET 12 #define DL0_SW_CLK_IN_FRC_ON_MASK 0x00001000 #define DL0_SW_CNT_CFG_DATA_OFFSET 4 #define DL0_SW_CNT_CFG_DATA_MASK 0x00000FF0 #define DL0_SW_CNT_CFG_PULSE_OFFSET 3 #define DL0_SW_CNT_CFG_PULSE_MASK 0x00000008 #define DL0_SW_EB_OFFSET 2 #define DL0_SW_EB_MASK 0x00000004 #define DL0_SW_CNT_PULSE_OFFSET 1 #define DL0_SW_CNT_PULSE_MASK 0x00000002 #define DL0_SW_OPERATION_OFFSET 0 #define DL0_SW_OPERATION_MASK 0x00000001 //----------------------------------- #define CFG_DDR_DELAYLINE1_CFG_ADDR 0x38 #define DL1_CNT_VALUE_OFFSET 16 #define DL1_CNT_VALUE_MASK 0x00FF0000 #define DL1_CNT_ADD_SUB_SEL_OFFSET 15 #define DL1_CNT_ADD_SUB_SEL_MASK 0x00008000 #define DL1_SW_CNT_SOFT_RST_OFFSET 14 #define DL1_SW_CNT_SOFT_RST_MASK 0x00004000 #define DL1_SW_CLK_OUT_FRC_ON_OFFSET 13 #define DL1_SW_CLK_OUT_FRC_ON_MASK 0x00002000 #define DL1_SW_CLK_IN_FRC_ON_OFFSET 12 #define DL1_SW_CLK_IN_FRC_ON_MASK 0x00001000 #define DL1_SW_CNT_CFG_DATA_OFFSET 4 #define DL1_SW_CNT_CFG_DATA_MASK 0x00000FF0 #define DL1_SW_CNT_CFG_PULSE_OFFSET 3 #define DL1_SW_CNT_CFG_PULSE_MASK 0x00000008 #define DL1_SW_EB_OFFSET 2 #define DL1_SW_EB_MASK 0x00000004 #define DL1_SW_CNT_PULSE_OFFSET 1 #define DL1_SW_CNT_PULSE_MASK 0x00000002 #define DL1_SW_OPERATION_OFFSET 0 #define DL1_SW_OPERATION_MASK 0x00000001 //----------------------------------- #define CFG_DDR_DELAYLINE2_CFG_ADDR 0x3C #define DL2_CNT_VALUE_OFFSET 16 #define DL2_CNT_VALUE_MASK 0x00FF0000 #define DL2_CNT_ADD_SUB_SEL_OFFSET 15 #define DL2_CNT_ADD_SUB_SEL_MASK 0x00008000 #define DL2_SW_CNT_SOFT_RST_OFFSET 14 #define DL2_SW_CNT_SOFT_RST_MASK 0x00004000 #define DL2_SW_CLK_OUT_FRC_ON_OFFSET 13 #define DL2_SW_CLK_OUT_FRC_ON_MASK 0x00002000 #define DL2_SW_CLK_IN_FRC_ON_OFFSET 12 #define DL2_SW_CLK_IN_FRC_ON_MASK 0x00001000 #define DL2_SW_CNT_CFG_DATA_OFFSET 4 #define DL2_SW_CNT_CFG_DATA_MASK 0x00000FF0 #define DL2_SW_CNT_CFG_PULSE_OFFSET 3 #define DL2_SW_CNT_CFG_PULSE_MASK 0x00000008 #define DL2_SW_EB_OFFSET 2 #define DL2_SW_EB_MASK 0x00000004 #define DL2_SW_CNT_PULSE_OFFSET 1 #define DL2_SW_CNT_PULSE_MASK 0x00000002 #define DL2_SW_OPERATION_OFFSET 0 #define DL2_SW_OPERATION_MASK 0x00000001 //----------------------------------- #define CFG_DDR_RXTX_RAM_CFG_ADDR 0x40 #define RXTX_RAM1_CLK_FRC_ON_OFFSET 1 #define RXTX_RAM1_CLK_FRC_ON_MASK 0x00000002 #define RXTX_RAM0_CLK_FRC_ON_OFFSET 0 #define RXTX_RAM0_CLK_FRC_ON_MASK 0x00000001 //----------------------------------- #define CFG_DDR_DBG_BUS0_ADDR 0xC0 #define DDR_DBG_BUS0_OFFSET 0 #define DDR_DBG_BUS0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DDR_DBG_BUS1_ADDR 0xC4 #define DDR_DBG_BUS1_OFFSET 0 #define DDR_DBG_BUS1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DDR_CHN_HUB_ST_ADDR 0xD0 #define CHN_ID_OFFSET 0 #define CHN_ID_MASK 0x0000000F //----------------------------------- #define CFG_DDR_DELAYLINE_DEMO_ST_ADDR 0xD4 #define DL0_DBG_BUS_OFFSET 0 #define DL0_DBG_BUS_MASK 0x0000FFFF //----------------------------------- #define CFG_DDR_DELAYLINE_ST_ADDR 0xD8 #define DL_DBG_BUS_OFFSET 0 #define DL_DBG_BUS_MASK 0x0000FFFF //----------------------------------- #define CFG_DDR_MEM_FIFO_ST_ADDR 0xE4 #define MEM_FIFO1_DATA_NUM_OFFSET 19 #define MEM_FIFO1_DATA_NUM_MASK 0x03F80000 #define MEM_FIFO1_PRE_FULL_OFFSET 18 #define MEM_FIFO1_PRE_FULL_MASK 0x00040000 #define MEM_FIFO1_FULL_OFFSET 17 #define MEM_FIFO1_FULL_MASK 0x00020000 #define MEM_FIFO1_EMP_OFFSET 16 #define MEM_FIFO1_EMP_MASK 0x00010000 #define MEM_FIFO0_DATA_NUM_OFFSET 3 #define MEM_FIFO0_DATA_NUM_MASK 0x000003F8 #define MEM_FIFO0_PRE_FULL_OFFSET 2 #define MEM_FIFO0_PRE_FULL_MASK 0x00000004 #define MEM_FIFO0_FULL_OFFSET 1 #define MEM_FIFO0_FULL_MASK 0x00000002 #define MEM_FIFO0_EMP_OFFSET 0 #define MEM_FIFO0_EMP_MASK 0x00000001 //----------------------------------- #define CFG_DDR_CMD_FIFO_ST_ADDR 0xE8 #define CMD_FIFO1_DATA_NUM_OFFSET 18 #define CMD_FIFO1_DATA_NUM_MASK 0x003C0000 #define CMD_FIFO1_FULL_OFFSET 17 #define CMD_FIFO1_FULL_MASK 0x00020000 #define CMD_FIFO1_EMP_OFFSET 16 #define CMD_FIFO1_EMP_MASK 0x00010000 #define CMD_FIFO0_DATA_NUM_OFFSET 2 #define CMD_FIFO0_DATA_NUM_MASK 0x0000003C #define CMD_FIFO0_FULL_OFFSET 1 #define CMD_FIFO0_FULL_MASK 0x00000002 #define CMD_FIFO0_EMP_OFFSET 0 #define CMD_FIFO0_EMP_MASK 0x00000001 //----------------------------------- #define CFG_DDR_INT_RAW_ADDR 0xF0 #define DDR_TRAINING_DEMO_DONE_INT_RAW_OFFSET 19 #define DDR_TRAINING_DEMO_DONE_INT_RAW_MASK 0x00080000 #define DDR_TRAINING_MONITIOR_FAIL_INT_RAW_OFFSET 18 #define DDR_TRAINING_MONITIOR_FAIL_INT_RAW_MASK 0x00040000 #define DDR_TRAINING_DONE_INT_RAW_OFFSET 17 #define DDR_TRAINING_DONE_INT_RAW_MASK 0x00020000 #define DDR_SW_CHN_INT_RAW_OFFSET 16 #define DDR_SW_CHN_INT_RAW_MASK 0x00010000 #define DDR_CHN8_INT_RAW_OFFSET 8 #define DDR_CHN8_INT_RAW_MASK 0x00000100 #define DDR_CHN7_INT_RAW_OFFSET 7 #define DDR_CHN7_INT_RAW_MASK 0x00000080 #define DDR_CHN6_INT_RAW_OFFSET 6 #define DDR_CHN6_INT_RAW_MASK 0x00000040 #define DDR_CHN5_INT_RAW_OFFSET 5 #define DDR_CHN5_INT_RAW_MASK 0x00000020 #define DDR_CHN4_INT_RAW_OFFSET 4 #define DDR_CHN4_INT_RAW_MASK 0x00000010 #define DDR_CHN3_INT_RAW_OFFSET 3 #define DDR_CHN3_INT_RAW_MASK 0x00000008 #define DDR_CHN2_INT_RAW_OFFSET 2 #define DDR_CHN2_INT_RAW_MASK 0x00000004 #define DDR_CHN1_INT_RAW_OFFSET 1 #define DDR_CHN1_INT_RAW_MASK 0x00000002 #define DDR_CHN0_INT_RAW_OFFSET 0 #define DDR_CHN0_INT_RAW_MASK 0x00000001 //----------------------------------- #define CFG_DDR_INT_ST_ADDR 0xF4 #define DDR_TRAINING_DEMO_DONE_INT_ST_OFFSET 19 #define DDR_TRAINING_DEMO_DONE_INT_ST_MASK 0x00080000 #define DDR_TRAINING_MONITIOR_FAIL_INT_ST_OFFSET 18 #define DDR_TRAINING_MONITIOR_FAIL_INT_ST_MASK 0x00040000 #define DDR_TRAINING_DONE_INT_ST_OFFSET 17 #define DDR_TRAINING_DONE_INT_ST_MASK 0x00020000 #define DDR_SW_CHN_INT_ST_OFFSET 16 #define DDR_SW_CHN_INT_ST_MASK 0x00010000 #define DDR_CHN8_INT_ST_OFFSET 8 #define DDR_CHN8_INT_ST_MASK 0x00000100 #define DDR_CHN7_INT_ST_OFFSET 7 #define DDR_CHN7_INT_ST_MASK 0x00000080 #define DDR_CHN6_INT_ST_OFFSET 6 #define DDR_CHN6_INT_ST_MASK 0x00000040 #define DDR_CHN5_INT_ST_OFFSET 5 #define DDR_CHN5_INT_ST_MASK 0x00000020 #define DDR_CHN4_INT_ST_OFFSET 4 #define DDR_CHN4_INT_ST_MASK 0x00000010 #define DDR_CHN3_INT_ST_OFFSET 3 #define DDR_CHN3_INT_ST_MASK 0x00000008 #define DDR_CHN2_INT_ST_OFFSET 2 #define DDR_CHN2_INT_ST_MASK 0x00000004 #define DDR_CHN1_INT_ST_OFFSET 1 #define DDR_CHN1_INT_ST_MASK 0x00000002 #define DDR_CHN0_INT_ST_OFFSET 0 #define DDR_CHN0_INT_ST_MASK 0x00000001 //----------------------------------- #define CFG_DDR_INT_ENA_ADDR 0xF8 #define DDR_TRAINING_DEMO_DONE_INT_ENA_OFFSET 19 #define DDR_TRAINING_DEMO_DONE_INT_ENA_MASK 0x00080000 #define DDR_TRAINING_MONITIOR_FAIL_INT_ENA_OFFSET 18 #define DDR_TRAINING_MONITIOR_FAIL_INT_ENA_MASK 0x00040000 #define DDR_TRAINING_DONE_INT_ENA_OFFSET 17 #define DDR_TRAINING_DONE_INT_ENA_MASK 0x00020000 #define DDR_SW_CHN_INT_ENA_OFFSET 16 #define DDR_SW_CHN_INT_ENA_MASK 0x00010000 #define DDR_CHN8_INT_ENA_OFFSET 8 #define DDR_CHN8_INT_ENA_MASK 0x00000100 #define DDR_CHN7_INT_ENA_OFFSET 7 #define DDR_CHN7_INT_ENA_MASK 0x00000080 #define DDR_CHN6_INT_ENA_OFFSET 6 #define DDR_CHN6_INT_ENA_MASK 0x00000040 #define DDR_CHN5_INT_ENA_OFFSET 5 #define DDR_CHN5_INT_ENA_MASK 0x00000020 #define DDR_CHN4_INT_ENA_OFFSET 4 #define DDR_CHN4_INT_ENA_MASK 0x00000010 #define DDR_CHN3_INT_ENA_OFFSET 3 #define DDR_CHN3_INT_ENA_MASK 0x00000008 #define DDR_CHN2_INT_ENA_OFFSET 2 #define DDR_CHN2_INT_ENA_MASK 0x00000004 #define DDR_CHN1_INT_ENA_OFFSET 1 #define DDR_CHN1_INT_ENA_MASK 0x00000002 #define DDR_CHN0_INT_ENA_OFFSET 0 #define DDR_CHN0_INT_ENA_MASK 0x00000001 //----------------------------------- #define CFG_DDR_INT_CLR_ADDR 0xFC #define DDR_TRAINING_DEMO_DONE_INT_CLR_OFFSET 19 #define DDR_TRAINING_DEMO_DONE_INT_CLR_MASK 0x00080000 #define DDR_TRAINING_MONITIOR_FAIL_INT_CLR_OFFSET 18 #define DDR_TRAINING_MONITIOR_FAIL_INT_CLR_MASK 0x00040000 #define DDR_TRAINING_DONE_INT_CLR_OFFSET 17 #define DDR_TRAINING_DONE_INT_CLR_MASK 0x00020000 #define DDR_SW_CHN_INT_CLR_OFFSET 16 #define DDR_SW_CHN_INT_CLR_MASK 0x00010000 #define DDR_CHN8_INT_CLR_OFFSET 8 #define DDR_CHN8_INT_CLR_MASK 0x00000100 #define DDR_CHN7_INT_CLR_OFFSET 7 #define DDR_CHN7_INT_CLR_MASK 0x00000080 #define DDR_CHN6_INT_CLR_OFFSET 6 #define DDR_CHN6_INT_CLR_MASK 0x00000040 #define DDR_CHN5_INT_CLR_OFFSET 5 #define DDR_CHN5_INT_CLR_MASK 0x00000020 #define DDR_CHN4_INT_CLR_OFFSET 4 #define DDR_CHN4_INT_CLR_MASK 0x00000010 #define DDR_CHN3_INT_CLR_OFFSET 3 #define DDR_CHN3_INT_CLR_MASK 0x00000008 #define DDR_CHN2_INT_CLR_OFFSET 2 #define DDR_CHN2_INT_CLR_MASK 0x00000004 #define DDR_CHN1_INT_CLR_OFFSET 1 #define DDR_CHN1_INT_CLR_MASK 0x00000002 #define DDR_CHN0_INT_CLR_OFFSET 0 #define DDR_CHN0_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_DDR_OPERATION_INT_MEM0_ADDR 0x100 #define SW_MEM_WDATA0_OFFSET 0 #define SW_MEM_WDATA0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DDR_OPERATION_INT_MEM1_ADDR 0x104 #define CMD_OR_DATA_FIFO_OFFSET 28 #define CMD_OR_DATA_FIFO_MASK 0x10000000 #define SW_MEM_WDATA1_OFFSET 0 #define SW_MEM_WDATA1_MASK 0x00FFFFFF //----------------------------------- #define CFG_DDR_OPERATION_INT_MEM2_ADDR 0x108 #define SW_MEM0_RDATA_OFFSET 0 #define SW_MEM0_RDATA_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DDR_OPERATION_INT_MEM3_ADDR 0x11C #define SW_RD_OR_WR_OFFSET 9 #define SW_RD_OR_WR_MASK 0x00000200 #define SW_MEM_HANDLE_EB_OFFSET 8 #define SW_MEM_HANDLE_EB_MASK 0x00000100 #define SW_MEM_WR_OFFSET 3 #define SW_MEM_WR_MASK 0x00000008 #define SW_SWH_CLK_PHY_90_270_OFFSET 2 #define SW_SWH_CLK_PHY_90_270_MASK 0x00000004 #define PHY_EB_SOFT_OFFSET 1 #define PHY_EB_SOFT_MASK 0x00000002 #define SW_MEM_RD_OFFSET 0 #define SW_MEM_RD_MASK 0x00000001 //----------------------------------- #define CFG_DDR_OPERATION_INT_MEM4_ADDR 0x120 #define SW_MEM1_RDATA_OFFSET 0 #define SW_MEM1_RDATA_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DDR_CHN0_CFG_ADDR 0x200 #define CHN0_PREFETCH_WORD_NUM_OFFSET 0 #define CHN0_PREFETCH_WORD_NUM_MASK 0x000000FF //----------------------------------- #define CFG_DDR_CHN1_CFG_ADDR 0x204 #define CHN1_PREFETCH_WORD_NUM_OFFSET 0 #define CHN1_PREFETCH_WORD_NUM_MASK 0x000000FF //----------------------------------- #define CFG_DDR_CHN2_CFG_ADDR 0x208 #define CHN2_PREFETCH_WORD_NUM_OFFSET 0 #define CHN2_PREFETCH_WORD_NUM_MASK 0x000000FF //----------------------------------- #define CFG_DDR_CHN3_CFG_ADDR 0x20C #define CHN3_PREFETCH_WORD_NUM_OFFSET 0 #define CHN3_PREFETCH_WORD_NUM_MASK 0x000000FF //----------------------------------- #define CFG_DDR_CHN4_CFG_ADDR 0x210 #define CHN4_PREFETCH_WORD_NUM_OFFSET 0 #define CHN4_PREFETCH_WORD_NUM_MASK 0x000000FF //----------------------------------- #define CFG_DDR_CHN5_CFG_ADDR 0x214 #define CHN5_PREFETCH_WORD_NUM_OFFSET 0 #define CHN5_PREFETCH_WORD_NUM_MASK 0x000000FF //----------------------------------- #define CFG_DDR_CHN6_CFG_ADDR 0x218 #define CHN6_PREFETCH_WORD_NUM_OFFSET 0 #define CHN6_PREFETCH_WORD_NUM_MASK 0x000000FF //HW module read/write macro #define DDR_RF_READ_REG(addr) SOC_READ_REG(DDR_RF_BASEADDR + addr) #define DDR_RF_WRITE_REG(addr,value) SOC_WRITE_REG(DDR_RF_BASEADDR + addr,value)