//----------------------------------- #define CFG_DSI_CTRL_RF_DSI_EN_ADDR 0x00 #define DSI_CTRL_RF_DSI_EN_OFFSET 0 #define DSI_CTRL_RF_DSI_EN_MASK 0x00000001 //----------------------------------- #define CFG_DSI_CTRL_RF_ESC_CLK_CFG_ADDR 0x04 #define DSI_CTRL_RF_ESC_CLK_DIVISOR_OFFSET 0 #define DSI_CTRL_RF_ESC_CLK_DIVISOR_MASK 0x000000FF //----------------------------------- #define CFG_DSI_CTRL_RF_VID_CMD_MODE_ADDR 0x08 #define DSI_CTRL_RF_VSYNC_MODE_OFFSET 3 #define DSI_CTRL_RF_VSYNC_MODE_MASK 0x00000008 #define DSI_CTRL_RF_VID_MODE_CONFIG_OFFSET 1 #define DSI_CTRL_RF_VID_MODE_CONFIG_MASK 0x00000006 #define DSI_CTRL_RF_VID_CMD_MODE_OFFSET 0 #define DSI_CTRL_RF_VID_CMD_MODE_MASK 0x00000001 //----------------------------------- #define CFG_DSI_CTRL_RF_VID_LP_CFG_ADDR 0x0c #define DSI_CTRL_RF_VSA_LP_EN_OFFSET 6 #define DSI_CTRL_RF_VSA_LP_EN_MASK 0x00000040 #define DSI_CTRL_RF_VBP_LP_EN_OFFSET 5 #define DSI_CTRL_RF_VBP_LP_EN_MASK 0x00000020 #define DSI_CTRL_RF_VACT_LP_EN_OFFSET 4 #define DSI_CTRL_RF_VACT_LP_EN_MASK 0x00000010 #define DSI_CTRL_RF_VFP_LP_EN_OFFSET 3 #define DSI_CTRL_RF_VFP_LP_EN_MASK 0x00000008 #define DSI_CTRL_RF_HBP_LP_EN_OFFSET 2 #define DSI_CTRL_RF_HBP_LP_EN_MASK 0x00000004 #define DSI_CTRL_RF_HFP_LP_EN_OFFSET 1 #define DSI_CTRL_RF_HFP_LP_EN_MASK 0x00000002 #define DSI_CTRL_RF_LPCMD_EN_OFFSET 0 #define DSI_CTRL_RF_LPCMD_EN_MASK 0x00000001 //----------------------------------- #define CFG_DSI_CTRL_RF_VID_BLANK_SIZE_ADDR 0x10 #define DSI_CTRL_RF_VSA_LINES_OFFSET 16 #define DSI_CTRL_RF_VSA_LINES_MASK 0x00FF0000 #define DSI_CTRL_RF_VBP_LINES_OFFSET 8 #define DSI_CTRL_RF_VBP_LINES_MASK 0x0000FF00 #define DSI_CTRL_RF_VFP_LINES_OFFSET 0 #define DSI_CTRL_RF_VFP_LINES_MASK 0x000000FF //----------------------------------- #define CFG_DSI_CTRL_RF_VID_VACT_SIZE_ADDR 0x14 #define DSI_CTRL_RF_VACT_LINES_OFFSET 0 #define DSI_CTRL_RF_VACT_LINES_MASK 0x0000FFFF //----------------------------------- #define CFG_DSI_CTRL_RF_VID_HLINE_SIZE1_ADDR 0x18 #define DSI_CTRL_RF_HBP_CYCLES_OFFSET 16 #define DSI_CTRL_RF_HBP_CYCLES_MASK 0x03FF0000 #define DSI_CTRL_RF_HAS_CYCLES_OFFSET 0 #define DSI_CTRL_RF_HAS_CYCLES_MASK 0x000003FF //----------------------------------- #define CFG_DSI_CTRL_RF_VID_HLINE_SIZE2_ADDR 0x1c #define DSI_CTRL_RF_HLINE_CYCLES_OFFSET 0 #define DSI_CTRL_RF_HLINE_CYCLES_MASK 0x0001FFFF //----------------------------------- #define CFG_DSI_CTRL_RF_VID_PKT_SIZE_ADDR 0x20 #define DSI_CTRL_RF_VID_CHUNK_NUM_OFFSET 16 #define DSI_CTRL_RF_VID_CHUNK_NUM_MASK 0x3FFF0000 #define DSI_CTRL_RF_VID_PKT_SIZE_OFFSET 0 #define DSI_CTRL_RF_VID_PKT_SIZE_MASK 0x0000FFFF //----------------------------------- #define CFG_DSI_CTRL_RF_VID_HACT_PIXELS_ADDR 0x24 #define DSI_CTRL_RF_HACT_PIXELS_OFFSET 0 #define DSI_CTRL_RF_HACT_PIXELS_MASK 0x00003FFF //----------------------------------- #define CFG_DSI_CTRL_RF_VID_NULL_PKT_SIZE_ADDR 0x28 #define DSI_CTRL_RF_NULL_PKT_SIZE_OFFSET 0 #define DSI_CTRL_RF_NULL_PKT_SIZE_MASK 0x0000FFFF //----------------------------------- #define CFG_DSI_CTRL_RF_VID_FORMAT_ADDR 0x2C #define DSI_CTRL_RF_VID_VCID_OFFSET 6 #define DSI_CTRL_RF_VID_VCID_MASK 0x000000C0 #define DSI_CTRL_RF_VID_FORMAT_OFFSET 0 #define DSI_CTRL_RF_VID_FORMAT_MASK 0x0000003F //----------------------------------- #define CFG_DSI_CTRL_RF_LANE_CFG_ADDR 0x30 #define DSI_CTRL_RF_NONCONTINUED_CLK_EN_OFFSET 5 #define DSI_CTRL_RF_NONCONTINUED_CLK_EN_MASK 0x00000020 #define DSI_CTRL_RF_TXREQUESTHS_CLK_OFFSET 4 #define DSI_CTRL_RF_TXREQUESTHS_CLK_MASK 0x00000010 #define DSI_CTRL_RF_ENABLE_CLK_OFFSET 3 #define DSI_CTRL_RF_ENABLE_CLK_MASK 0x00000008 #define DSI_CTRL_RF_ENABLE_PHY_OFFSET 2 #define DSI_CTRL_RF_ENABLE_PHY_MASK 0x00000004 #define DSI_CTRL_RF_LANE_NUM_OFFSET 0 #define DSI_CTRL_RF_LANE_NUM_MASK 0x00000003 //----------------------------------- #define CFG_DSI_CTRL_RF_PHY_TIMING_CFG_ADDR 0x34 #define DSI_CTRL_RF_PHY_LP2HS_TIME_OFFSET 16 #define DSI_CTRL_RF_PHY_LP2HS_TIME_MASK 0x03FF0000 #define DSI_CTRL_RF_PHY_HS2LP_TIME_OFFSET 0 #define DSI_CTRL_RF_PHY_HS2LP_TIME_MASK 0x000003FF //----------------------------------- #define CFG_DSI_CTRL_RF_CMD_MODE_CFG_ADDR 0x38 #define DSI_CTRL_RF_LP_SEND_CMOFF_OFFSET 19 #define DSI_CTRL_RF_LP_SEND_CMOFF_MASK 0x00080000 #define DSI_CTRL_RF_LP_SEND_CMON_OFFSET 18 #define DSI_CTRL_RF_LP_SEND_CMON_MASK 0x00040000 #define DSI_CTRL_RF_LP_SEND_SHDN_OFFSET 17 #define DSI_CTRL_RF_LP_SEND_SHDN_MASK 0x00020000 #define DSI_CTRL_RF_LP_SEND_TURNON_OFFSET 16 #define DSI_CTRL_RF_LP_SEND_TURNON_MASK 0x00010000 #define DSI_CTRL_RF_LP_SEND_GSWR0_OFFSET 15 #define DSI_CTRL_RF_LP_SEND_GSWR0_MASK 0x00008000 #define DSI_CTRL_RF_LP_SEND_GSWR1_OFFSET 14 #define DSI_CTRL_RF_LP_SEND_GSWR1_MASK 0x00004000 #define DSI_CTRL_RF_LP_SEND_GSWR2_OFFSET 13 #define DSI_CTRL_RF_LP_SEND_GSWR2_MASK 0x00002000 #define DSI_CTRL_RF_LP_SEND_GRD0_OFFSET 12 #define DSI_CTRL_RF_LP_SEND_GRD0_MASK 0x00001000 #define DSI_CTRL_RF_LP_SEND_GRD1_OFFSET 11 #define DSI_CTRL_RF_LP_SEND_GRD1_MASK 0x00000800 #define DSI_CTRL_RF_LP_SEND_GRD2_OFFSET 10 #define DSI_CTRL_RF_LP_SEND_GRD2_MASK 0x00000400 #define DSI_CTRL_RF_LP_SEND_DSWR0_OFFSET 9 #define DSI_CTRL_RF_LP_SEND_DSWR0_MASK 0x00000200 #define DSI_CTRL_RF_LP_SEND_DSWR1_OFFSET 8 #define DSI_CTRL_RF_LP_SEND_DSWR1_MASK 0x00000100 #define DSI_CTRL_RF_LP_SEND_DRD0_OFFSET 7 #define DSI_CTRL_RF_LP_SEND_DRD0_MASK 0x00000080 #define DSI_CTRL_RF_LP_SEND_EXEQ_OFFSET 6 #define DSI_CTRL_RF_LP_SEND_EXEQ_MASK 0x00000040 #define DSI_CTRL_RF_LP_SEND_SET_MAX_OFFSET 5 #define DSI_CTRL_RF_LP_SEND_SET_MAX_MASK 0x00000020 #define DSI_CTRL_RF_LP_SEND_NULL_PKT_OFFSET 4 #define DSI_CTRL_RF_LP_SEND_NULL_PKT_MASK 0x00000010 #define DSI_CTRL_RF_LP_SEND_BLANK_PKT_OFFSET 3 #define DSI_CTRL_RF_LP_SEND_BLANK_PKT_MASK 0x00000008 #define DSI_CTRL_RF_LP_SEND_GLWR_OFFSET 2 #define DSI_CTRL_RF_LP_SEND_GLWR_MASK 0x00000004 #define DSI_CTRL_RF_LP_SEND_DLWR_OFFSET 1 #define DSI_CTRL_RF_LP_SEND_DLWR_MASK 0x00000002 #define DSI_CTRL_RF_LP_SEND_PPS_OFFSET 0 #define DSI_CTRL_RF_LP_SEND_PPS_MASK 0x00000001 //----------------------------------- #define CFG_DSI_CTRL_RF_CMD_HDR_ADDR 0x40 #define DSI_CTRL_RF_CMD_WC_OFFSET 8 #define DSI_CTRL_RF_CMD_WC_MASK 0x00FFFF00 #define DSI_CTRL_RF_CMD_VCID_OFFSET 6 #define DSI_CTRL_RF_CMD_VCID_MASK 0x000000C0 #define DSI_CTRL_RF_CMD_DT_OFFSET 0 #define DSI_CTRL_RF_CMD_DT_MASK 0x0000003F //----------------------------------- #define CFG_DSI_CTRL_RF_CMD_PAYLOAD_ADDR 0x44 #define DSI_CTRL_RF_CMD_PAYLOAD_OFFSET 0 #define DSI_CTRL_RF_CMD_PAYLOAD_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DSI_CTRL_RF_PHY_STATUS_ADDR 0x48 #define DSI_CTRL_RF_STOPSTATE_CLK_OFFSET 5 #define DSI_CTRL_RF_STOPSTATE_CLK_MASK 0x00000020 #define DSI_CTRL_RF_STOPSTATE_LANE3_OFFSET 4 #define DSI_CTRL_RF_STOPSTATE_LANE3_MASK 0x00000010 #define DSI_CTRL_RF_STOPSTATE_LANE2_OFFSET 3 #define DSI_CTRL_RF_STOPSTATE_LANE2_MASK 0x00000008 #define DSI_CTRL_RF_STOPSTATE_LANE1_OFFSET 2 #define DSI_CTRL_RF_STOPSTATE_LANE1_MASK 0x00000004 #define DSI_CTRL_RF_STOPSTATE_LANE0_OFFSET 1 #define DSI_CTRL_RF_STOPSTATE_LANE0_MASK 0x00000002 #define DSI_CTRL_RF_PHY_DIRECTION_OFFSET 0 #define DSI_CTRL_RF_PHY_DIRECTION_MASK 0x00000001 //----------------------------------- #define CFG_DSI_CTRL_RF_TX_CTRL_ADDR 0x4c #define DSI_CTRL_RF_FORCE_STOP_OFFSET 5 #define DSI_CTRL_RF_FORCE_STOP_MASK 0x00000020 #define DSI_CTRL_RF_DATA_LANE_ULPS_EXIT_OFFSET 4 #define DSI_CTRL_RF_DATA_LANE_ULPS_EXIT_MASK 0x00000010 #define DSI_CTRL_RF_DATA_LANE_ULPS_ENTER_OFFSET 3 #define DSI_CTRL_RF_DATA_LANE_ULPS_ENTER_MASK 0x00000008 #define DSI_CTRL_RF_CLK_LANE_ULPS_EXIT_OFFSET 2 #define DSI_CTRL_RF_CLK_LANE_ULPS_EXIT_MASK 0x00000004 #define DSI_CTRL_RF_CLK_LANE_ULPS_ENTER_OFFSET 1 #define DSI_CTRL_RF_CLK_LANE_ULPS_ENTER_MASK 0x00000002 #define DSI_CTRL_RF_EOTP_EN_OFFSET 0 #define DSI_CTRL_RF_EOTP_EN_MASK 0x00000001 //----------------------------------- #define CFG_DSI_CTRL_RF_CMD_RD_DATA_ADDR 0x50 #define DSI_CTRL_RF_CMD_RD_DATA_OFFSET 0 #define DSI_CTRL_RF_CMD_RD_DATA_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DSI_CTRL_RF_FIFO_STATUS_ADDR 0x54 #define DSI_CTRL_RF_CMD_FIFO_EMPTY_OFFSET 7 #define DSI_CTRL_RF_CMD_FIFO_EMPTY_MASK 0x00000080 #define DSI_CTRL_RF_CMD_FIFO_FULL_OFFSET 6 #define DSI_CTRL_RF_CMD_FIFO_FULL_MASK 0x00000040 #define DSI_CTRL_RF_DATA_FIFO_EMPTY_OFFSET 5 #define DSI_CTRL_RF_DATA_FIFO_EMPTY_MASK 0x00000020 #define DSI_CTRL_RF_DATA_FIFO_FULL_OFFSET 4 #define DSI_CTRL_RF_DATA_FIFO_FULL_MASK 0x00000010 #define DSI_CTRL_RF_RD_FIFO_EMPTY_OFFSET 3 #define DSI_CTRL_RF_RD_FIFO_EMPTY_MASK 0x00000008 #define DSI_CTRL_RF_RD_FIFO_FULL_OFFSET 2 #define DSI_CTRL_RF_RD_FIFO_FULL_MASK 0x00000004 #define DSI_CTRL_RF_PIXEL_FIFO_EMPTY_OFFSET 1 #define DSI_CTRL_RF_PIXEL_FIFO_EMPTY_MASK 0x00000002 #define DSI_CTRL_RF_PIXEL_FIFO_FULL_OFFSET 0 #define DSI_CTRL_RF_PIXEL_FIFO_FULL_MASK 0x00000001 //----------------------------------- #define CFG_DSI_CTRL_RF_CMD_STATUS_ADDR 0x58 #define DSI_CTRL_RF_RD_CMD_DONE_OFFSET 1 #define DSI_CTRL_RF_RD_CMD_DONE_MASK 0x00000002 #define DSI_CTRL_RF_RD_CMD_ONGOING_OFFSET 0 #define DSI_CTRL_RF_RD_CMD_ONGOING_MASK 0x00000001 //----------------------------------- #define CFG_DSI_CTRL_RF_PATTERN_GEN_CFG_ADDR 0x5C #define DSI_CTRL_RF_PATERN_FORMAT_OFFSET 25 #define DSI_CTRL_RF_PATERN_FORMAT_MASK 0x06000000 #define DSI_CTRL_RF_PATTERN_GEN_EN_OFFSET 24 #define DSI_CTRL_RF_PATTERN_GEN_EN_MASK 0x01000000 #define DSI_CTRL_RF_PATTERN_PIXEL_OFFSET 0 #define DSI_CTRL_RF_PATTERN_PIXEL_MASK 0x00FFFFFF //----------------------------------- #define CFG_DSI_CTRL_RF_LPCMD_BYTE_LIMIT_ADDR 0x60 #define DSI_CTRL_RF_LPCMD_BYTE_LIMIT_OFFSET 0 #define DSI_CTRL_RF_LPCMD_BYTE_LIMIT_MASK 0x0000FFFF //----------------------------------- #define CFG_DSI_CTRL_RF_MAX_RD_TIME_ADDR 0x64 #define DSI_CTRL_RF_MAX_RD_TIME_OFFSET 0 #define DSI_CTRL_RF_MAX_RD_TIME_MASK 0x0001FFFF //----------------------------------- #define CFG_DSI_CTRL_RF_RESERVED_REG0_ADDR 0x90 #define DSI_CTRL_RF_RES_REG0_OFFSET 0 #define DSI_CTRL_RF_RES_REG0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DSI_CTRL_RF_RESERVED_REG1_ADDR 0x94 #define DSI_CTRL_RF_RES_REG1_OFFSET 0 #define DSI_CTRL_RF_RES_REG1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DSI_CTRL_RF_DSI_INT_ENA_ADDR 0xA0 #define DSI_CTRL_RF_DSI_ERR31_INT_ENA_OFFSET 31 #define DSI_CTRL_RF_DSI_ERR31_INT_ENA_MASK 0x80000000 #define DSI_CTRL_RF_DSI_ERR30_INT_ENA_OFFSET 30 #define DSI_CTRL_RF_DSI_ERR30_INT_ENA_MASK 0x40000000 #define DSI_CTRL_RF_DSI_ERR29_INT_ENA_OFFSET 29 #define DSI_CTRL_RF_DSI_ERR29_INT_ENA_MASK 0x20000000 #define DSI_CTRL_RF_DSI_ERR28_INT_ENA_OFFSET 28 #define DSI_CTRL_RF_DSI_ERR28_INT_ENA_MASK 0x10000000 #define DSI_CTRL_RF_DSI_ERR27_INT_ENA_OFFSET 27 #define DSI_CTRL_RF_DSI_ERR27_INT_ENA_MASK 0x08000000 #define DSI_CTRL_RF_DSI_ERR26_INT_ENA_OFFSET 26 #define DSI_CTRL_RF_DSI_ERR26_INT_ENA_MASK 0x04000000 #define DSI_CTRL_RF_DSI_ERR25_INT_ENA_OFFSET 25 #define DSI_CTRL_RF_DSI_ERR25_INT_ENA_MASK 0x02000000 #define DSI_CTRL_RF_DSI_ERR24_INT_ENA_OFFSET 24 #define DSI_CTRL_RF_DSI_ERR24_INT_ENA_MASK 0x01000000 #define DSI_CTRL_RF_DSI_ERR23_INT_ENA_OFFSET 23 #define DSI_CTRL_RF_DSI_ERR23_INT_ENA_MASK 0x00800000 #define DSI_CTRL_RF_DSI_ERR22_INT_ENA_OFFSET 22 #define DSI_CTRL_RF_DSI_ERR22_INT_ENA_MASK 0x00400000 #define DSI_CTRL_RF_DSI_ERR21_INT_ENA_OFFSET 21 #define DSI_CTRL_RF_DSI_ERR21_INT_ENA_MASK 0x00200000 #define DSI_CTRL_RF_DSI_ERR20_INT_ENA_OFFSET 20 #define DSI_CTRL_RF_DSI_ERR20_INT_ENA_MASK 0x00100000 #define DSI_CTRL_RF_DSI_ERR19_INT_ENA_OFFSET 19 #define DSI_CTRL_RF_DSI_ERR19_INT_ENA_MASK 0x00080000 #define DSI_CTRL_RF_DSI_ERR18_INT_ENA_OFFSET 18 #define DSI_CTRL_RF_DSI_ERR18_INT_ENA_MASK 0x00040000 #define DSI_CTRL_RF_DSI_ERR17_INT_ENA_OFFSET 17 #define DSI_CTRL_RF_DSI_ERR17_INT_ENA_MASK 0x00020000 #define DSI_CTRL_RF_DSI_ERR16_INT_ENA_OFFSET 16 #define DSI_CTRL_RF_DSI_ERR16_INT_ENA_MASK 0x00010000 #define DSI_CTRL_RF_DSI_ERR15_INT_ENA_OFFSET 15 #define DSI_CTRL_RF_DSI_ERR15_INT_ENA_MASK 0x00008000 #define DSI_CTRL_RF_DSI_ERR14_INT_ENA_OFFSET 14 #define DSI_CTRL_RF_DSI_ERR14_INT_ENA_MASK 0x00004000 #define DSI_CTRL_RF_DSI_ERR13_INT_ENA_OFFSET 13 #define DSI_CTRL_RF_DSI_ERR13_INT_ENA_MASK 0x00002000 #define DSI_CTRL_RF_DSI_ERR12_INT_ENA_OFFSET 12 #define DSI_CTRL_RF_DSI_ERR12_INT_ENA_MASK 0x00001000 #define DSI_CTRL_RF_DSI_ERR11_INT_ENA_OFFSET 11 #define DSI_CTRL_RF_DSI_ERR11_INT_ENA_MASK 0x00000800 #define DSI_CTRL_RF_DSI_ERR10_INT_ENA_OFFSET 10 #define DSI_CTRL_RF_DSI_ERR10_INT_ENA_MASK 0x00000400 #define DSI_CTRL_RF_DSI_ERR9_INT_ENA_OFFSET 9 #define DSI_CTRL_RF_DSI_ERR9_INT_ENA_MASK 0x00000200 #define DSI_CTRL_RF_DSI_ERR8_INT_ENA_OFFSET 8 #define DSI_CTRL_RF_DSI_ERR8_INT_ENA_MASK 0x00000100 #define DSI_CTRL_RF_DSI_ERR7_INT_ENA_OFFSET 7 #define DSI_CTRL_RF_DSI_ERR7_INT_ENA_MASK 0x00000080 #define DSI_CTRL_RF_DSI_ERR6_INT_ENA_OFFSET 6 #define DSI_CTRL_RF_DSI_ERR6_INT_ENA_MASK 0x00000040 #define DSI_CTRL_RF_DSI_ERR5_INT_ENA_OFFSET 5 #define DSI_CTRL_RF_DSI_ERR5_INT_ENA_MASK 0x00000020 #define DSI_CTRL_RF_DSI_ERR4_INT_ENA_OFFSET 4 #define DSI_CTRL_RF_DSI_ERR4_INT_ENA_MASK 0x00000010 #define DSI_CTRL_RF_DSI_ERR3_INT_ENA_OFFSET 3 #define DSI_CTRL_RF_DSI_ERR3_INT_ENA_MASK 0x00000008 #define DSI_CTRL_RF_DSI_ERR2_INT_ENA_OFFSET 2 #define DSI_CTRL_RF_DSI_ERR2_INT_ENA_MASK 0x00000004 #define DSI_CTRL_RF_DSI_ERR1_INT_ENA_OFFSET 1 #define DSI_CTRL_RF_DSI_ERR1_INT_ENA_MASK 0x00000002 #define DSI_CTRL_RF_DSI_ERR0_INT_ENA_OFFSET 0 #define DSI_CTRL_RF_DSI_ERR0_INT_ENA_MASK 0x00000001 //----------------------------------- #define CFG_DSI_CTRL_RF_DSI_INT_CLR_ADDR 0xA4 #define DSI_CTRL_RF_DSI_ERR31_INT_CLR_OFFSET 31 #define DSI_CTRL_RF_DSI_ERR31_INT_CLR_MASK 0x80000000 #define DSI_CTRL_RF_DSI_ERR30_INT_CLR_OFFSET 30 #define DSI_CTRL_RF_DSI_ERR30_INT_CLR_MASK 0x40000000 #define DSI_CTRL_RF_DSI_ERR29_INT_CLR_OFFSET 29 #define DSI_CTRL_RF_DSI_ERR29_INT_CLR_MASK 0x20000000 #define DSI_CTRL_RF_DSI_ERR28_INT_CLR_OFFSET 28 #define DSI_CTRL_RF_DSI_ERR28_INT_CLR_MASK 0x10000000 #define DSI_CTRL_RF_DSI_ERR27_INT_CLR_OFFSET 27 #define DSI_CTRL_RF_DSI_ERR27_INT_CLR_MASK 0x08000000 #define DSI_CTRL_RF_DSI_ERR26_INT_CLR_OFFSET 26 #define DSI_CTRL_RF_DSI_ERR26_INT_CLR_MASK 0x04000000 #define DSI_CTRL_RF_DSI_ERR25_INT_CLR_OFFSET 25 #define DSI_CTRL_RF_DSI_ERR25_INT_CLR_MASK 0x02000000 #define DSI_CTRL_RF_DSI_ERR24_INT_CLR_OFFSET 24 #define DSI_CTRL_RF_DSI_ERR24_INT_CLR_MASK 0x01000000 #define DSI_CTRL_RF_DSI_ERR23_INT_CLR_OFFSET 23 #define DSI_CTRL_RF_DSI_ERR23_INT_CLR_MASK 0x00800000 #define DSI_CTRL_RF_DSI_ERR22_INT_CLR_OFFSET 22 #define DSI_CTRL_RF_DSI_ERR22_INT_CLR_MASK 0x00400000 #define DSI_CTRL_RF_DSI_ERR21_INT_CLR_OFFSET 21 #define DSI_CTRL_RF_DSI_ERR21_INT_CLR_MASK 0x00200000 #define DSI_CTRL_RF_DSI_ERR20_INT_CLR_OFFSET 20 #define DSI_CTRL_RF_DSI_ERR20_INT_CLR_MASK 0x00100000 #define DSI_CTRL_RF_DSI_ERR19_INT_CLR_OFFSET 19 #define DSI_CTRL_RF_DSI_ERR19_INT_CLR_MASK 0x00080000 #define DSI_CTRL_RF_DSI_ERR18_INT_CLR_OFFSET 18 #define DSI_CTRL_RF_DSI_ERR18_INT_CLR_MASK 0x00040000 #define DSI_CTRL_RF_DSI_ERR17_INT_CLR_OFFSET 17 #define DSI_CTRL_RF_DSI_ERR17_INT_CLR_MASK 0x00020000 #define DSI_CTRL_RF_DSI_ERR16_INT_CLR_OFFSET 16 #define DSI_CTRL_RF_DSI_ERR16_INT_CLR_MASK 0x00010000 #define DSI_CTRL_RF_DSI_ERR15_INT_CLR_OFFSET 15 #define DSI_CTRL_RF_DSI_ERR15_INT_CLR_MASK 0x00008000 #define DSI_CTRL_RF_DSI_ERR14_INT_CLR_OFFSET 14 #define DSI_CTRL_RF_DSI_ERR14_INT_CLR_MASK 0x00004000 #define DSI_CTRL_RF_DSI_ERR13_INT_CLR_OFFSET 13 #define DSI_CTRL_RF_DSI_ERR13_INT_CLR_MASK 0x00002000 #define DSI_CTRL_RF_DSI_ERR12_INT_CLR_OFFSET 12 #define DSI_CTRL_RF_DSI_ERR12_INT_CLR_MASK 0x00001000 #define DSI_CTRL_RF_DSI_ERR11_INT_CLR_OFFSET 11 #define DSI_CTRL_RF_DSI_ERR11_INT_CLR_MASK 0x00000800 #define DSI_CTRL_RF_DSI_ERR10_INT_CLR_OFFSET 10 #define DSI_CTRL_RF_DSI_ERR10_INT_CLR_MASK 0x00000400 #define DSI_CTRL_RF_DSI_ERR9_INT_CLR_OFFSET 9 #define DSI_CTRL_RF_DSI_ERR9_INT_CLR_MASK 0x00000200 #define DSI_CTRL_RF_DSI_ERR8_INT_CLR_OFFSET 8 #define DSI_CTRL_RF_DSI_ERR8_INT_CLR_MASK 0x00000100 #define DSI_CTRL_RF_DSI_ERR7_INT_CLR_OFFSET 7 #define DSI_CTRL_RF_DSI_ERR7_INT_CLR_MASK 0x00000080 #define DSI_CTRL_RF_DSI_ERR6_INT_CLR_OFFSET 6 #define DSI_CTRL_RF_DSI_ERR6_INT_CLR_MASK 0x00000040 #define DSI_CTRL_RF_DSI_ERR5_INT_CLR_OFFSET 5 #define DSI_CTRL_RF_DSI_ERR5_INT_CLR_MASK 0x00000020 #define DSI_CTRL_RF_DSI_ERR4_INT_CLR_OFFSET 4 #define DSI_CTRL_RF_DSI_ERR4_INT_CLR_MASK 0x00000010 #define DSI_CTRL_RF_DSI_ERR3_INT_CLR_OFFSET 3 #define DSI_CTRL_RF_DSI_ERR3_INT_CLR_MASK 0x00000008 #define DSI_CTRL_RF_DSI_ERR2_INT_CLR_OFFSET 2 #define DSI_CTRL_RF_DSI_ERR2_INT_CLR_MASK 0x00000004 #define DSI_CTRL_RF_DSI_ERR1_INT_CLR_OFFSET 1 #define DSI_CTRL_RF_DSI_ERR1_INT_CLR_MASK 0x00000002 #define DSI_CTRL_RF_DSI_ERR0_INT_CLR_OFFSET 0 #define DSI_CTRL_RF_DSI_ERR0_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_DSI_CTRL_RF_DSI_INT_RAW_ADDR 0xA8 #define DSI_CTRL_RF_DSI_ERR31_INT_RAW_OFFSET 31 #define DSI_CTRL_RF_DSI_ERR31_INT_RAW_MASK 0x80000000 #define DSI_CTRL_RF_DSI_ERR30_INT_RAW_OFFSET 30 #define DSI_CTRL_RF_DSI_ERR30_INT_RAW_MASK 0x40000000 #define DSI_CTRL_RF_DSI_ERR29_INT_RAW_OFFSET 29 #define DSI_CTRL_RF_DSI_ERR29_INT_RAW_MASK 0x20000000 #define DSI_CTRL_RF_DSI_ERR28_INT_RAW_OFFSET 28 #define DSI_CTRL_RF_DSI_ERR28_INT_RAW_MASK 0x10000000 #define DSI_CTRL_RF_DSI_ERR27_INT_RAW_OFFSET 27 #define DSI_CTRL_RF_DSI_ERR27_INT_RAW_MASK 0x08000000 #define DSI_CTRL_RF_DSI_ERR26_INT_RAW_OFFSET 26 #define DSI_CTRL_RF_DSI_ERR26_INT_RAW_MASK 0x04000000 #define DSI_CTRL_RF_DSI_ERR25_INT_RAW_OFFSET 25 #define DSI_CTRL_RF_DSI_ERR25_INT_RAW_MASK 0x02000000 #define DSI_CTRL_RF_DSI_ERR24_INT_RAW_OFFSET 24 #define DSI_CTRL_RF_DSI_ERR24_INT_RAW_MASK 0x01000000 #define DSI_CTRL_RF_DSI_ERR23_INT_RAW_OFFSET 23 #define DSI_CTRL_RF_DSI_ERR23_INT_RAW_MASK 0x00800000 #define DSI_CTRL_RF_DSI_ERR22_INT_RAW_OFFSET 22 #define DSI_CTRL_RF_DSI_ERR22_INT_RAW_MASK 0x00400000 #define DSI_CTRL_RF_DSI_ERR21_INT_RAW_OFFSET 21 #define DSI_CTRL_RF_DSI_ERR21_INT_RAW_MASK 0x00200000 #define DSI_CTRL_RF_DSI_ERR20_INT_RAW_OFFSET 20 #define DSI_CTRL_RF_DSI_ERR20_INT_RAW_MASK 0x00100000 #define DSI_CTRL_RF_DSI_ERR19_INT_RAW_OFFSET 19 #define DSI_CTRL_RF_DSI_ERR19_INT_RAW_MASK 0x00080000 #define DSI_CTRL_RF_DSI_ERR18_INT_RAW_OFFSET 18 #define DSI_CTRL_RF_DSI_ERR18_INT_RAW_MASK 0x00040000 #define DSI_CTRL_RF_DSI_ERR17_INT_RAW_OFFSET 17 #define DSI_CTRL_RF_DSI_ERR17_INT_RAW_MASK 0x00020000 #define DSI_CTRL_RF_DSI_ERR16_INT_RAW_OFFSET 16 #define DSI_CTRL_RF_DSI_ERR16_INT_RAW_MASK 0x00010000 #define DSI_CTRL_RF_DSI_ERR15_INT_RAW_OFFSET 15 #define DSI_CTRL_RF_DSI_ERR15_INT_RAW_MASK 0x00008000 #define DSI_CTRL_RF_DSI_ERR14_INT_RAW_OFFSET 14 #define DSI_CTRL_RF_DSI_ERR14_INT_RAW_MASK 0x00004000 #define DSI_CTRL_RF_DSI_ERR13_INT_RAW_OFFSET 13 #define DSI_CTRL_RF_DSI_ERR13_INT_RAW_MASK 0x00002000 #define DSI_CTRL_RF_DSI_ERR12_INT_RAW_OFFSET 12 #define DSI_CTRL_RF_DSI_ERR12_INT_RAW_MASK 0x00001000 #define DSI_CTRL_RF_DSI_ERR11_INT_RAW_OFFSET 11 #define DSI_CTRL_RF_DSI_ERR11_INT_RAW_MASK 0x00000800 #define DSI_CTRL_RF_DSI_ERR10_INT_RAW_OFFSET 10 #define DSI_CTRL_RF_DSI_ERR10_INT_RAW_MASK 0x00000400 #define DSI_CTRL_RF_DSI_ERR9_INT_RAW_OFFSET 9 #define DSI_CTRL_RF_DSI_ERR9_INT_RAW_MASK 0x00000200 #define DSI_CTRL_RF_DSI_ERR8_INT_RAW_OFFSET 8 #define DSI_CTRL_RF_DSI_ERR8_INT_RAW_MASK 0x00000100 #define DSI_CTRL_RF_DSI_ERR7_INT_RAW_OFFSET 7 #define DSI_CTRL_RF_DSI_ERR7_INT_RAW_MASK 0x00000080 #define DSI_CTRL_RF_DSI_ERR6_INT_RAW_OFFSET 6 #define DSI_CTRL_RF_DSI_ERR6_INT_RAW_MASK 0x00000040 #define DSI_CTRL_RF_DSI_ERR5_INT_RAW_OFFSET 5 #define DSI_CTRL_RF_DSI_ERR5_INT_RAW_MASK 0x00000020 #define DSI_CTRL_RF_DSI_ERR4_INT_RAW_OFFSET 4 #define DSI_CTRL_RF_DSI_ERR4_INT_RAW_MASK 0x00000010 #define DSI_CTRL_RF_DSI_ERR3_INT_RAW_OFFSET 3 #define DSI_CTRL_RF_DSI_ERR3_INT_RAW_MASK 0x00000008 #define DSI_CTRL_RF_DSI_ERR2_INT_RAW_OFFSET 2 #define DSI_CTRL_RF_DSI_ERR2_INT_RAW_MASK 0x00000004 #define DSI_CTRL_RF_DSI_ERR1_INT_RAW_OFFSET 1 #define DSI_CTRL_RF_DSI_ERR1_INT_RAW_MASK 0x00000002 #define DSI_CTRL_RF_DSI_ERR0_INT_RAW_OFFSET 0 #define DSI_CTRL_RF_DSI_ERR0_INT_RAW_MASK 0x00000001 //----------------------------------- #define CFG_DSI_CTRL_RF_DSI_INT_ST_ADDR 0xAC #define DSI_CTRL_RF_DSI_ERR31_INT_ST_OFFSET 31 #define DSI_CTRL_RF_DSI_ERR31_INT_ST_MASK 0x80000000 #define DSI_CTRL_RF_DSI_ERR30_INT_ST_OFFSET 30 #define DSI_CTRL_RF_DSI_ERR30_INT_ST_MASK 0x40000000 #define DSI_CTRL_RF_DSI_ERR29_INT_ST_OFFSET 29 #define DSI_CTRL_RF_DSI_ERR29_INT_ST_MASK 0x20000000 #define DSI_CTRL_RF_DSI_ERR28_INT_ST_OFFSET 28 #define DSI_CTRL_RF_DSI_ERR28_INT_ST_MASK 0x10000000 #define DSI_CTRL_RF_DSI_ERR27_INT_ST_OFFSET 27 #define DSI_CTRL_RF_DSI_ERR27_INT_ST_MASK 0x08000000 #define DSI_CTRL_RF_DSI_ERR26_INT_ST_OFFSET 26 #define DSI_CTRL_RF_DSI_ERR26_INT_ST_MASK 0x04000000 #define DSI_CTRL_RF_DSI_ERR25_INT_ST_OFFSET 25 #define DSI_CTRL_RF_DSI_ERR25_INT_ST_MASK 0x02000000 #define DSI_CTRL_RF_DSI_ERR24_INT_ST_OFFSET 24 #define DSI_CTRL_RF_DSI_ERR24_INT_ST_MASK 0x01000000 #define DSI_CTRL_RF_DSI_ERR23_INT_ST_OFFSET 23 #define DSI_CTRL_RF_DSI_ERR23_INT_ST_MASK 0x00800000 #define DSI_CTRL_RF_DSI_ERR22_INT_ST_OFFSET 22 #define DSI_CTRL_RF_DSI_ERR22_INT_ST_MASK 0x00400000 #define DSI_CTRL_RF_DSI_ERR21_INT_ST_OFFSET 21 #define DSI_CTRL_RF_DSI_ERR21_INT_ST_MASK 0x00200000 #define DSI_CTRL_RF_DSI_ERR20_INT_ST_OFFSET 20 #define DSI_CTRL_RF_DSI_ERR20_INT_ST_MASK 0x00100000 #define DSI_CTRL_RF_DSI_ERR19_INT_ST_OFFSET 19 #define DSI_CTRL_RF_DSI_ERR19_INT_ST_MASK 0x00080000 #define DSI_CTRL_RF_DSI_ERR18_INT_ST_OFFSET 18 #define DSI_CTRL_RF_DSI_ERR18_INT_ST_MASK 0x00040000 #define DSI_CTRL_RF_DSI_ERR17_INT_ST_OFFSET 17 #define DSI_CTRL_RF_DSI_ERR17_INT_ST_MASK 0x00020000 #define DSI_CTRL_RF_DSI_ERR16_INT_ST_OFFSET 16 #define DSI_CTRL_RF_DSI_ERR16_INT_ST_MASK 0x00010000 #define DSI_CTRL_RF_DSI_ERR15_INT_ST_OFFSET 15 #define DSI_CTRL_RF_DSI_ERR15_INT_ST_MASK 0x00008000 #define DSI_CTRL_RF_DSI_ERR14_INT_ST_OFFSET 14 #define DSI_CTRL_RF_DSI_ERR14_INT_ST_MASK 0x00004000 #define DSI_CTRL_RF_DSI_ERR13_INT_ST_OFFSET 13 #define DSI_CTRL_RF_DSI_ERR13_INT_ST_MASK 0x00002000 #define DSI_CTRL_RF_DSI_ERR12_INT_ST_OFFSET 12 #define DSI_CTRL_RF_DSI_ERR12_INT_ST_MASK 0x00001000 #define DSI_CTRL_RF_DSI_ERR11_INT_ST_OFFSET 11 #define DSI_CTRL_RF_DSI_ERR11_INT_ST_MASK 0x00000800 #define DSI_CTRL_RF_DSI_ERR10_INT_ST_OFFSET 10 #define DSI_CTRL_RF_DSI_ERR10_INT_ST_MASK 0x00000400 #define DSI_CTRL_RF_DSI_ERR9_INT_ST_OFFSET 9 #define DSI_CTRL_RF_DSI_ERR9_INT_ST_MASK 0x00000200 #define DSI_CTRL_RF_DSI_ERR8_INT_ST_OFFSET 8 #define DSI_CTRL_RF_DSI_ERR8_INT_ST_MASK 0x00000100 #define DSI_CTRL_RF_DSI_ERR7_INT_ST_OFFSET 7 #define DSI_CTRL_RF_DSI_ERR7_INT_ST_MASK 0x00000080 #define DSI_CTRL_RF_DSI_ERR6_INT_ST_OFFSET 6 #define DSI_CTRL_RF_DSI_ERR6_INT_ST_MASK 0x00000040 #define DSI_CTRL_RF_DSI_ERR5_INT_ST_OFFSET 5 #define DSI_CTRL_RF_DSI_ERR5_INT_ST_MASK 0x00000020 #define DSI_CTRL_RF_DSI_ERR4_INT_ST_OFFSET 4 #define DSI_CTRL_RF_DSI_ERR4_INT_ST_MASK 0x00000010 #define DSI_CTRL_RF_DSI_ERR3_INT_ST_OFFSET 3 #define DSI_CTRL_RF_DSI_ERR3_INT_ST_MASK 0x00000008 #define DSI_CTRL_RF_DSI_ERR2_INT_ST_OFFSET 2 #define DSI_CTRL_RF_DSI_ERR2_INT_ST_MASK 0x00000004 #define DSI_CTRL_RF_DSI_ERR1_INT_ST_OFFSET 1 #define DSI_CTRL_RF_DSI_ERR1_INT_ST_MASK 0x00000002 #define DSI_CTRL_RF_DSI_ERR0_INT_ST_OFFSET 0 #define DSI_CTRL_RF_DSI_ERR0_INT_ST_MASK 0x00000001 //HW module read/write macro #define DSI_CTRL_RF_READ_REG(addr) SOC_READ_REG(DSI_CTRL_RF_BASEADDR + addr) #define DSI_CTRL_RF_WRITE_REG(addr,value) SOC_WRITE_REG(DSI_CTRL_RF_BASEADDR + addr,value)