//----------------------------------- #define CFG_EFUSE_BITS32_0_ADDR 0x0000 #define VENDOR_CHECK_SUM_OFFSET 0 #define VENDOR_CHECK_SUM_MASK 0x000000FF #define PKG_VERSION_OFFSET 8 #define PKG_VERSION_MASK 0x0000FF00 #define VENDOR_EFUSE_PROG_DONE_OFFSET 16 #define VENDOR_EFUSE_PROG_DONE_MASK 0x00010000 #define VENDOR_EFUSE_TEST_DONE_OFFSET 17 #define VENDOR_EFUSE_TEST_DONE_MASK 0x00020000 #define VENDOR_BOND_VLD_OFFSET 18 #define VENDOR_BOND_VLD_MASK 0x00040000 #define VENDOR_SFC_CFG_VLD_OFFSET 19 #define VENDOR_SFC_CFG_VLD_MASK 0x00080000 #define VENDOR_EFUSE_PROG_DONE_BACKUP_OFFSET 20 #define VENDOR_EFUSE_PROG_DONE_BACKUP_MASK 0x00100000 #define VENDOR_EFUSE_TEST_DONE_BACKUP_OFFSET 21 #define VENDOR_EFUSE_TEST_DONE_BACKUP_MASK 0x00200000 #define VENDOR_BOND_VLD_BACKUP_OFFSET 22 #define VENDOR_BOND_VLD_BACKUP_MASK 0x00400000 #define VENDOR_SFC_CFG_VLD_BACKUP_OFFSET 23 #define VENDOR_SFC_CFG_VLD_BACKUP_MASK 0x00800000 #define BOND_ETH_ENA_OFFSET 24 #define BOND_ETH_ENA_MASK 0x01000000 #define BOND_ETH_TTE_ENA_OFFSET 25 #define BOND_ETH_TTE_ENA_MASK 0x02000000 #define BOND_ADA_ENA_OFFSET 26 #define BOND_ADA_ENA_MASK 0x04000000 #define BOND_MAC_PHY_ENA_OFFSET 27 #define BOND_MAC_PHY_ENA_MASK 0x08000000 #define BOND_ECC_SM2_ENA_OFFSET 28 #define BOND_ECC_SM2_ENA_MASK 0x10000000 #define BOND_SM3_ENA_OFFSET 29 #define BOND_SM3_ENA_MASK 0x20000000 #define BOND_SM4_ENA_OFFSET 30 #define BOND_SM4_ENA_MASK 0x40000000 #define BOND_AES128_ENA_OFFSET 31 #define BOND_AES128_ENA_MASK 0x80000000 //----------------------------------- #define CFG_EFUSE_BITS32_1_ADDR 0x0004 #define BOND_AES192_ENA_OFFSET 0 #define BOND_AES192_ENA_MASK 0x00000001 #define BOND_AES256_ENA_OFFSET 1 #define BOND_AES256_ENA_MASK 0x00000002 #define BOND_SHA_224_256_ENA_OFFSET 2 #define BOND_SHA_224_256_ENA_MASK 0x00000004 #define BOND_SHA_384_512_ENA_OFFSET 3 #define BOND_SHA_384_512_ENA_MASK 0x00000008 #define BOND_CHACHA_POLY_ENA_OFFSET 4 #define BOND_CHACHA_POLY_ENA_MASK 0x00000010 #define BOND_SEC_FLASH_ENA_OFFSET 5 #define BOND_SEC_FLASH_ENA_MASK 0x00000020 #define BOND_SEC_BOOT_ENA_OFFSET 6 #define BOND_SEC_BOOT_ENA_MASK 0x00000040 #define BOND_GREEN_PHY_ENA_OFFSET 7 #define BOND_GREEN_PHY_ENA_MASK 0x00000080 #define BOND_NEW_SG_ENA_OFFSET 8 #define BOND_NEW_SG_ENA_MASK 0x00000100 #define BOND_GD_SG_ENA_OFFSET 9 #define BOND_GD_SG_ENA_MASK 0x00000200 #define BOND_BAND0_ENA_OFFSET 10 #define BOND_BAND0_ENA_MASK 0x00000400 #define BOND_BAND1_ENA_OFFSET 11 #define BOND_BAND1_ENA_MASK 0x00000800 #define BOND_SR_ENA_OFFSET 12 #define BOND_SR_ENA_MASK 0x00001000 #define BOND_QR_ENA_OFFSET 13 #define BOND_QR_ENA_MASK 0x00002000 #define BOND_XR_ENA_OFFSET 14 #define BOND_XR_ENA_MASK 0x00004000 #define BOND_16QAM_ENA_OFFSET 15 #define BOND_16QAM_ENA_MASK 0x00008000 #define BOND_DPSK_ENA_OFFSET 16 #define BOND_DPSK_ENA_MASK 0x00010000 #define BOND_FSK_ENA_OFFSET 17 #define BOND_FSK_ENA_MASK 0x00020000 #define BOND_1618_CRATE_ENA_OFFSET 18 #define BOND_1618_CRATE_ENA_MASK 0x00040000 #define BOND_NEW_SG_FREQ_EXTEND_OFFSET 19 #define BOND_NEW_SG_FREQ_EXTEND_MASK 0x00080000 #define BOND_CPU0_ENA_OFFSET 20 #define BOND_CPU0_ENA_MASK 0x00100000 #define BOND_IIS_ENA_OFFSET 21 #define BOND_IIS_ENA_MASK 0x00200000 #define BOND_ETH_ENA_BACKUP_OFFSET 24 #define BOND_ETH_ENA_BACKUP_MASK 0x01000000 #define BOND_ETH_TTE_ENA_BACKUP_OFFSET 25 #define BOND_ETH_TTE_ENA_BACKUP_MASK 0x02000000 #define BOND_ADA_ENA_BACKUP_OFFSET 26 #define BOND_ADA_ENA_BACKUP_MASK 0x04000000 #define BOND_MAC_PHY_ENA_BACKUP_OFFSET 27 #define BOND_MAC_PHY_ENA_BACKUP_MASK 0x08000000 #define BOND_ECC_SM2_ENA_BACKUP_OFFSET 28 #define BOND_ECC_SM2_ENA_BACKUP_MASK 0x10000000 #define BOND_SM3_ENA_BACKUP_OFFSET 29 #define BOND_SM3_ENA_BACKUP_MASK 0x20000000 #define BOND_SM4_ENA_BACKUP_OFFSET 30 #define BOND_SM4_ENA_BACKUP_MASK 0x40000000 #define BOND_AES128_ENA_BACKUP_OFFSET 31 #define BOND_AES128_ENA_BACKUP_MASK 0x80000000 //----------------------------------- #define CFG_EFUSE_BITS32_2_ADDR 0x0008 #define BOND_AES192_ENA_BACKUP_OFFSET 0 #define BOND_AES192_ENA_BACKUP_MASK 0x00000001 #define BOND_AES256_ENA_BACKUP_OFFSET 1 #define BOND_AES256_ENA_BACKUP_MASK 0x00000002 #define BOND_SHA_224_256_ENA_BACKUP_OFFSET 2 #define BOND_SHA_224_256_ENA_BACKUP_MASK 0x00000004 #define BOND_SHA_384_512_ENA_BACKUP_OFFSET 3 #define BOND_SHA_384_512_ENA_BACKUP_MASK 0x00000008 #define BOND_CHACHA_POLY_ENA_BACKUP_OFFSET 4 #define BOND_CHACHA_POLY_ENA_BACKUP_MASK 0x00000010 #define BOND_SEC_FLASH_ENA_BACKUP_OFFSET 5 #define BOND_SEC_FLASH_ENA_BACKUP_MASK 0x00000020 #define BOND_SEC_BOOT_ENA_BACKUP_OFFSET 6 #define BOND_SEC_BOOT_ENA_BACKUP_MASK 0x00000040 #define BOND_GREEN_PHY_ENA_BACKUP_OFFSET 7 #define BOND_GREEN_PHY_ENA_BACKUP_MASK 0x00000080 #define BOND_NEW_SG_ENA_BACKUP_OFFSET 8 #define BOND_NEW_SG_ENA_BACKUP_MASK 0x00000100 #define BOND_GD_SG_ENA_BACKUP_OFFSET 9 #define BOND_GD_SG_ENA_BACKUP_MASK 0x00000200 #define BOND_BAND0_ENA_BACKUP_OFFSET 10 #define BOND_BAND0_ENA_BACKUP_MASK 0x00000400 #define BOND_BAND1_ENA_BACKUP_OFFSET 11 #define BOND_BAND1_ENA_BACKUP_MASK 0x00000800 #define BOND_SR_ENA_BACKUP_OFFSET 12 #define BOND_SR_ENA_BACKUP_MASK 0x00001000 #define BOND_QR_ENA_BACKUP_OFFSET 13 #define BOND_QR_ENA_BACKUP_MASK 0x00002000 #define BOND_XR_ENA_BACKUP_OFFSET 14 #define BOND_XR_ENA_BACKUP_MASK 0x00004000 #define BOND_16QAM_ENA_BACKUP_OFFSET 15 #define BOND_16QAM_ENA_BACKUP_MASK 0x00008000 #define BOND_DPSK_ENA_BACKUP_OFFSET 16 #define BOND_DPSK_ENA_BACKUP_MASK 0x00010000 #define BOND_FSK_ENA_BACKUP_OFFSET 17 #define BOND_FSK_ENA_BACKUP_MASK 0x00020000 #define BOND_1618_CRATE_ENA_BACKUP_OFFSET 18 #define BOND_1618_CRATE_ENA_BACKUP_MASK 0x00040000 #define BOND_NEW_SG_FREQ_EXTEND_BACKUP_OFFSET 19 #define BOND_NEW_SG_FREQ_EXTEND_BACKUP_MASK 0x00080000 #define BOND_CPU0_ENA_BACKUP_OFFSET 20 #define BOND_CPU0_ENA_BACKUP_MASK 0x00100000 #define BOND_IIS_ENA_BACKUP_OFFSET 21 #define BOND_IIS_ENA_BACKUP_MASK 0x00200000 #define MAC_ADDR_B0_OFFSET 24 #define MAC_ADDR_B0_MASK 0xFF000000 //----------------------------------- #define CFG_EFUSE_BITS32_3_ADDR 0x000C #define MAC_ADDR_B1_OFFSET 0 #define MAC_ADDR_B1_MASK 0x000000FF #define MAC_ADDR_B2_OFFSET 8 #define MAC_ADDR_B2_MASK 0x0000FF00 #define MAC_ADDR_B3_OFFSET 16 #define MAC_ADDR_B3_MASK 0x00FF0000 #define MAC_ADDR_B4_OFFSET 24 #define MAC_ADDR_B4_MASK 0xFF000000 //----------------------------------- #define CFG_EFUSE_BITS32_4_ADDR 0x0010 #define MAC_ADDR_B5_OFFSET 0 #define MAC_ADDR_B5_MASK 0x000000FF #define SFC_CLK_BOND_OFFSET 8 #define SFC_CLK_BOND_MASK 0x0000FF00 #define SFC_CSN_BOND_OFFSET 16 #define SFC_CSN_BOND_MASK 0x00FF0000 #define SFC_D0_BOND_OFFSET 24 #define SFC_D0_BOND_MASK 0xFF000000 //----------------------------------- #define CFG_EFUSE_BITS32_5_ADDR 0x0014 #define SFC_D1_BOND_OFFSET 0 #define SFC_D1_BOND_MASK 0x000000FF #define SFC_D2_BOND_OFFSET 8 #define SFC_D2_BOND_MASK 0x0000FF00 #define SFC_D3_BOND_OFFSET 16 #define SFC_D3_BOND_MASK 0x00FF0000 #define FLASH_READ_CMD_OFFSET 24 #define FLASH_READ_CMD_MASK 0xFF000000 //----------------------------------- #define CFG_EFUSE_BITS32_6_ADDR 0x0018 #define FLASH_ENA_CMD_OFFSET 0 #define FLASH_ENA_CMD_MASK 0x000000FF #define FLASH_RESET_CMD_OFFSET 8 #define FLASH_RESET_CMD_MASK 0x0000FF00 #define FLASH_CMD_VLD_OFFSET 16 #define FLASH_CMD_VLD_MASK 0x00010000 #define ANA_TRIM_PARA_F0_OFFSET 17 #define ANA_TRIM_PARA_F0_MASK 0xFFFE0000 //----------------------------------- #define CFG_EFUSE_BITS32_7_ADDR 0x001C #define ANA_TRIM_PARA_F1_OFFSET 0 #define ANA_TRIM_PARA_F1_MASK 0x07FFFFFF #define FLASH_CMD_VLD_BACKUP_OFFSET 27 #define FLASH_CMD_VLD_BACKUP_MASK 0x08000000 #define REV_VERSION_OFFSET 28 #define REV_VERSION_MASK 0xF0000000 //----------------------------------- #define CFG_EFUSE_BITS32_8_ADDR 0x0020 #define USR_CHECK_SUM_OFFSET 0 #define USR_CHECK_SUM_MASK 0x0000FFFF #define USR_GLB_CFG_OFFSET 16 #define USR_GLB_CFG_MASK 0xFFFF0000 //----------------------------------- #define CFG_EFUSE_BITS32_9_ADDR 0x0024 #define USR_CFG_OFFSET 0 #define USR_CFG_MASK 0xFFFFFFFF //----------------------------------- #define CFG_EFUSE_BITS32_10_ADDR 0x0028 //----------------------------------- #define CFG_EFUSE_BITS32_11_ADDR 0x002C #define EFUSE_METER_BG_CORE_CA_OFFSET 0 #define EFUSE_METER_BG_CORE_CA_MASK 0x0000001F #define EFUSE_METER_BG_CORE_CB_OFFSET 5 #define EFUSE_METER_BG_CORE_CB_MASK 0x000001E0 #define EFUSE_METER_BG_BG_CA_OFFSET 9 #define EFUSE_METER_BG_BG_CA_MASK 0x00003E00 #define EFUSE_METER_BG_BG_CB_OFFSET 14 #define EFUSE_METER_BG_BG_CB_MASK 0x0003C000 #define EFUSE_METER_CRC_OFFSET 24 #define EFUSE_METER_CRC_MASK 0xFF000000 //----------------------------------- #define CFG_EFUSE_BITS32_12_ADDR 0x0030 #define ANA_TRIM_BG_ICCAL_OFFSET 8 #define ANA_TRIM_BG_ICCAL_MASK 0x00001F00 #define ANA_TRIM_CRC_OFFSET 24 #define ANA_TRIM_CRC_MASK 0xFF000000 //----------------------------------- #define CFG_EFUSE_BITS32_13_ADDR 0x0034 #define ANA_TRIM_DCDC_OFFSET 5 #define ANA_TRIM_DCDC_MASK 0x000001E0 #define ANA_TRIM_PMU_LDO_OFFSET 9 #define ANA_TRIM_PMU_LDO_MASK 0x00001E00 //----------------------------------- #define CFG_EFUSE_BITS32_14_ADDR 0x0038 #define WAFER_LOT_ID_7_OFFSET 0 #define WAFER_LOT_ID_7_MASK 0x000001FF #define WAFER_LOT_ID_6_OFFSET 9 #define WAFER_LOT_ID_6_MASK 0x0000FE00 #define WAFER_LOT_ID_5_OFFSET 16 #define WAFER_LOT_ID_5_MASK 0x00FF0000 #define WAFER_LOT_ID_4_OFFSET 24 #define WAFER_LOT_ID_4_MASK 0xFF000000 //----------------------------------- #define CFG_EFUSE_BITS32_15_ADDR 0x003C #define WAFER_POS_Y_OFFSET 0 #define WAFER_POS_Y_MASK 0x000000FF #define WAFER_POS_X_OFFSET 8 #define WAFER_POS_X_MASK 0x0000FF00 #define WAFER_ID_OFFSET 16 #define WAFER_ID_MASK 0x00FF0000 #define WAFER_LOT_ID_3_OFFSET 24 #define WAFER_LOT_ID_3_MASK 0xFF000000 //----------------------------------- #define CFG_EFUSE_BITS32_63_ADDR 0x00F4 #define ATE_MTER_BG_ICCAL_PARA_OFFSET 0 #define ATE_MTER_BG_ICCAL_PARA_MASK 0x0000001F #define ATE_MTER_PARA_CRC_OFFSET 24 #define ATE_MTER_PARA_CRC_MASK 0xFF000000 //HW module read/write macro #define EFUSE_MAPPING_READ_REG(addr) SOC_READ_REG(EFUSE_MAPPING_BASEADDR + addr) #define EFUSE_MAPPING_WRITE_REG(addr,value) SOC_WRITE_REG(EFUSE_MAPPING_BASEADDR + addr,value)