//-----------------------------------
#define CFG_MAC_INT_ADDR 0x0000
#define ZC2_REPORT_OFFSET 30
#define ZC2_REPORT_MASK 0x40000000
#define ZC1_REPORT_OFFSET 29
#define ZC1_REPORT_MASK 0x20000000
#define SCH_REQ_INT_OFFSET 28
#define SCH_REQ_INT_MASK 0x10000000
#define NTB_COMM_INT3_OFFSET 27
#define NTB_COMM_INT3_MASK 0x08000000
#define NTB_COMM_INT2_OFFSET 26
#define NTB_COMM_INT2_MASK 0x04000000
#define NTB_COMM_INT1_OFFSET 25
#define NTB_COMM_INT1_MASK 0x02000000
#define NTB_COMM_INT0_OFFSET 24
#define NTB_COMM_INT0_MASK 0x01000000
#define PHY_RX_TIMEOUT_OFFSET 23
#define PHY_RX_TIMEOUT_MASK 0x00800000
#define MAC_RX_ABORT_OFFSET 22
#define MAC_RX_ABORT_MASK 0x00400000
#define TX_RD_PB_BUF_ERR_OFFSET 21
#define TX_RD_PB_BUF_ERR_MASK 0x00200000
#define TX_RD_PB_DESC_ERR_OFFSET 20
#define TX_RD_PB_DESC_ERR_MASK 0x00100000
#define ZC_UP_BOUND_OFFSET 19
#define ZC_UP_BOUND_MASK 0x00080000
#define ZC_LOW_BOUND_OFFSET 18
#define ZC_LOW_BOUND_MASK 0x00040000
#define TX_AES_ERR_OFFSET 17
#define TX_AES_ERR_MASK 0x00020000
#define ZC_REPORT_OFFSET 16
#define ZC_REPORT_MASK 0x00010000
#define LOW_WATERMARK_OFFSET 15
#define LOW_WATERMARK_MASK 0x00008000
#define RX_PAYLOAD_OVERFLOW_OFFSET 14
#define RX_PAYLOAD_OVERFLOW_MASK 0x00004000
#define RX_DESC_OVERFLOW_OFFSET 13
#define RX_DESC_OVERFLOW_MASK 0x00002000
#define FC_RX_OFFSET 12
#define FC_RX_MASK 0x00001000
#define PB_RX_OFFSET 11
#define PB_RX_MASK 0x00000800
#define MPDU_RX_OFFSET 10
#define MPDU_RX_MASK 0x00000400
#define TX_UNDERRUN_OFFSET 9
#define TX_UNDERRUN_MASK 0x00000200
#define END_DESC_ERR_OFFSET 8
#define END_DESC_ERR_MASK 0x00000100
#define START_DESCERR_OFFSET 7
#define START_DESCERR_MASK 0x00000080
#define MAC_BUS_ERROR_OFFSET 6
#define MAC_BUS_ERROR_MASK 0x00000040
#define MPDU_TX_DONE_OFFSET 5
#define MPDU_TX_DONE_MASK 0x00000020
#define HWQ_STOPPED_OFFSET 4
#define HWQ_STOPPED_MASK 0x00000010
#define SCH_STOP_OFFSET 3
#define SCH_STOP_MASK 0x00000008
#define BEACON_RECEIVED_OFFSET 2
#define BEACON_RECEIVED_MASK 0x00000004
#define BEACON_MISSED_OFFSET 1
#define BEACON_MISSED_MASK 0x00000002
#define BEACON_ALERT_OFFSET 0
#define BEACON_ALERT_MASK 0x00000001

//HW module read/write macro
#define RGF_MAC_INT_READ_REG(addr) SOC_READ_REG(RGF_MAC_INT_BASEADDR + addr)
#define RGF_MAC_INT_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_MAC_INT_BASEADDR + addr,value)