//-----------------------------------
#define CFG_ITR_ITR_SRC_CTRL0_ADDR 0x0000
#define ITR_SRC_WIDTH_OFFSET 16
#define ITR_SRC_WIDTH_MASK 0x07FF0000
#define ITR_SRC_HEIGHT_OFFSET 0
#define ITR_SRC_HEIGHT_MASK 0x000007FF

//-----------------------------------
#define CFG_ITR_ITR_SRC_CTRL1_ADDR 0x0004
#define ITR_SRC_BASE_ADDRESS_OFFSET 0
#define ITR_SRC_BASE_ADDRESS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_ITR_ITR_DST_CTRL0_ADDR 0x0008
#define ITR_CLOCKWISE_OFFSET 0
#define ITR_CLOCKWISE_MASK 0x00000001

//-----------------------------------
#define CFG_ITR_ITR_DST_CTRL1_ADDR 0x000C
#define ITR_DST_BASE_ADDRESS_OFFSET 0
#define ITR_DST_BASE_ADDRESS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_ITR_ITR_GLB_CTRL_ADDR 0x0010
#define ITR_STATUS_OFFSET 31
#define ITR_STATUS_MASK 0x80000000
#define ITR_START_OFFSET 0
#define ITR_START_MASK 0x00000001

//-----------------------------------
#define CFG_ITR_ITR_INT_CLR_ADDR 0x0014
#define ITR_INT_CLR_OFFSET 0
#define ITR_INT_CLR_MASK 0x00000001

//HW module read/write macro
#define RGF_TRANSPOSE_READ_REG(addr) SOC_READ_REG(RGF_TRANSPOSE_BASEADDR + addr)
#define RGF_TRANSPOSE_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_TRANSPOSE_BASEADDR + addr,value)