/**************************************************************************** Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED. This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT be copied by any method or incorporated into another program without the express written consent of Aerospace C.Power. This Information or any portion thereof remains the property of Aerospace C.Power. The Information contained herein is believed to be accurate and Aerospace C.Power assumes no responsibility or liability for its use in any way and conveys no license or title under any patent or copyright and makes no representation or warranty that this Information is free from patent or copyright infringement. ****************************************************************************/ #ifndef __PHY_ISR_H #define __PHY_ISR_H /* os shim includes */ #include "os_types.h" /* driver includes */ #include "iot_irq.h" #include "os_timer_api.h" #ifdef __cplusplus extern "C" { #endif #define IRQ_NUM_PHY_LIC_OVR_STRESS HAL_VECTOR_PHY_1 /* phy interrupt map */ #define PHY_TX_FD_TX_DONE (0x1 << 0) //bit 0 #define PHY_FD_TX_ABORT (0x1 << 1) //bit 1 #define PHY_FD_TX_STUCK (0x1 << 2) //bit 2 #define PHY_TX_TD_START (0x1 << 3) //bit 3 #define PHY_TX_TD_FC_DONE (0x1 << 5) //bit 5 #define PHY_TX_FD_INSERT_PREAM_DONE (0x1 << 6) //bit 6 #define PHY_LIC_OVR_STRESS (0x1 << 9) //bit 9 #define PHY_RECV_FD_CH_EST_DONE (0x1 << 16) //bit 16 #define PHY_RECV_FD_FC_OK (0x1 << 17) //bit 17 #define PHY_RECV_FD_FC_FAIL (0x1 << 18) //bit 18 #define PHY_RECV_FD_PB_OK (0x1 << 19) //bit 19 #define PHY_RECV_FD_PB_FAIL (0x1 << 20) //bit 20 #define PHY_RECV_FD_PLD_OK (0x1 << 21) //bit 21 #define PHY_RECV_FD_PLD_FAIL (0x1 << 22) //bit 22 #define PHY_RECV_FC_RAW_RECEIVE (0x1 << 30) //bit 30 #define INTR_TYPE_PHY_FD_FC_OK (0x1 << 0) #define INTR_TYPE_PHY_FD_FC_FAIL (0x1 << 1) #define INTR_TYPE_PHY_TX_FD_TX_DONE (0x1 << 2) #define INTR_TYPE_PHY_LIC_OVR_STRESS (0x1 << 5) #if MAC_SYM_NUM_FIX || MAC_TIMESTAMPING || ENA_CCO_RX_THR_PHASE_CHANGE #define INTR_TYPE_PHY_FD_PLD_OK (0x1 << 3) #define INTR_TYPE_PHY_FD_PLD_FAIL (0x1 << 4) #endif #define INTR_TYPE_PHY_FD_TX_ABORT (0x1 << 6) #define INTR_TYPE_PHY_TX_TD_START (0x1 << 7) #define INTR_TYPE_PHY_FD_TX_STUCK (0x1 << 8) #define INTR_TYPE_PHY_INSERT_PREAM_DONE (0x1 << 9) #define INTR_TYPE_PHY_FD_CH_EST_DONE (0x1 << 10) #define INTR_TYPE_PHY_FD_PB_OK (0x1 << 11) #define INTR_TYPE_PHY_FD_PB_FAIL (0x1 << 12) #define INTR_TYPE_PHY_FC_RAW_RECEIVE (0x1 << 13) #define INTR_TYPE_PHY_TX_TD_FC_DONE (0x1 << 14) /** * @brief phy_overstress_is_on * get the overstress status * * @param [none] * * @return [true or false] */ bool_t phy_overstress_is_on(void); /** * @brief phy_overstress_power_up * increase tx power with full level. * * @param void [void] * * @return [none] */ void phy_overstress_power_up(); /** * @brief phy_isr_init() -init phy isr. */ void phy_isr_init(); /** * @brief phy_isr_start() -start phy isr. */ void phy_isr_start(); /** * @brief phy_isr_start_cpu1() - enable and start cpu1 phy interrupt * * @param none * * @return none */ void phy_isr_start_cpu1(void); #ifdef __cplusplus } #endif #endif