/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/
#include "os_types.h"
#include "hw_war.h"
#include "phy_bb.h"
#include "phy_multi_ppm.h"
#include "hw_phy_api.h"

#if ENA_SYNC_DIFF_CCO_PPM

void phy_multi_sync_ppm_rst(phy_ppm_status_ctxt_t *ctxt)
{
    IOT_ASSERT(ctxt != NULL);
    for (uint8_t idx = 0; idx < MAX_SYNC_CCO_CNT; idx++) {
        ctxt->ppm_status[idx].rsv = 0;
        ctxt->ppm_status[idx].valid = 0;
        ctxt->ppm_status[idx].nid = 0;
        ctxt->ppm_status[idx].ppm_err = 0;
    }
}

void* phy_multi_sync_get_ppm_status()
{
    return &g_phy_cpu_share_ctxt.ppm_status;
}

uint32_t phy_multi_sync_get_record_nid(phy_ppm_status_ctxt_t *ctxt,
    uint8_t idx)
{
    if (idx >= MAX_SYNC_CCO_CNT || ctxt == NULL) {
        IOT_ASSERT(0);
    }

    return ctxt->ppm_status[idx].nid;
}

void phy_multi_sync_set_record_nid(phy_ppm_status_ctxt_t *ctxt,
    uint8_t idx, uint32_t nid)
{
    if (idx >= MAX_SYNC_CCO_CNT || ctxt == NULL) {
        IOT_ASSERT(0);
    }

    ctxt->ppm_status[idx].nid = nid;
    return;
}

uint32_t phy_multi_sync_get_valid_flag(phy_ppm_status_ctxt_t *ctxt,
    uint8_t idx)
{
    if (idx >= MAX_SYNC_CCO_CNT || ctxt == NULL) {
        IOT_ASSERT(0);
    }

    return ctxt->ppm_status[idx].valid;
}

void phy_multi_sync_set_valid_flag(phy_ppm_status_ctxt_t *ctxt,
    uint8_t idx, uint8_t valid)
{
    /* mac and phy share this flag */
    if (idx >= MAX_SYNC_CCO_CNT || ctxt == NULL) {
        IOT_ASSERT(0);
    }

    ctxt->ppm_status[idx].valid = valid;
    return;
}

int16_t phy_multi_sync_get_record_ppm(phy_ppm_status_ctxt_t *ctxt,
    uint8_t idx)
{
    if (idx >= MAX_SYNC_CCO_CNT || ctxt == NULL) {
        IOT_ASSERT(0);
    }
    if (phy_multi_sync_get_valid_flag(ctxt, idx) == RECORD_PPM_VALID) {
        return ctxt->ppm_status[idx].ppm_err;
    } else {
        return PLC_MAX_MAC_NTB_PPM;
    }

}

void phy_multi_sync_set_record_ppm(phy_ppm_status_ctxt_t *ctxt,
    uint8_t idx, int16_t ppm)
{
    if (idx >= MAX_SYNC_CCO_CNT || ctxt == NULL) {
        IOT_ASSERT(0);
    }

    ctxt->ppm_status[idx].ppm_err = ppm;
    return;
}

uint8_t phy_multi_sync_get_record_idx(phy_ppm_status_ctxt_t *ctxt,
    uint32_t cur_nid)
{
    uint8_t idx = MAX_SYNC_CCO_CNT;
    for (idx = 0; idx < MAX_SYNC_CCO_CNT; idx++) {
        if (phy_multi_sync_get_valid_flag(ctxt, idx) != RECORD_PPM_INVALID_NID
            && phy_multi_sync_get_record_nid(ctxt, idx) == cur_nid) {
            break;
        }
    }

    return idx;
}

void phy_multi_sync_set_enable(phy_ppm_status_ctxt_t *ctxt, uint8_t enable)
{
    ctxt->enable = !!enable;
}

void phy_multi_sync_apply_bb_ppm(phy_ppm_status_ctxt_t *ctxt,
    uint32_t cur_nid, uint8_t update_flag)
{
    uint8_t idx;
    int16_t ppm_err;
    if (ctxt->enable == 0) {
        return;
    }

    idx = phy_multi_sync_get_record_idx(ctxt, cur_nid);
    if (idx < MAX_SYNC_CCO_CNT) {
        ppm_err = phy_multi_sync_get_record_ppm(ctxt, idx)
            >> PLC_NTB_PPM_SHIFT;
        if (ppm_err != PLC_MAX_PPM_SUPPORT) {
            ppm_err = phy_ppm_cal_hw_val(PHY_CAL_UNIT_1_1, -ppm_err, 0);
        } else {
            ppm_err = g_phy_cpu_share_ctxt.phy_ppm_init;
        }
    } else {
        /* Note: rx fc nid is PLC_DBG_PKT_MODE_NID/PLC_NID_INVALID/unknow nid,
         * then set ppm is phy default.
         */
        ppm_err = g_phy_cpu_share_ctxt.phy_ppm_init;
    }

    phy_ppm_set(ppm_err, update_flag);
}

uint32_t phy_multi_sync_set_ppm(phy_ppm_status_ctxt_t *status_ctxt, uint32_t nid)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t ret = ERR_INVAL;
    /* kl2 use hw multippm */
    uint8_t idx = phy_multi_sync_get_record_idx(status_ctxt, nid);
    if (idx < MAX_SYNC_CCO_CNT) {
        ret = phy_set_sw_nn_ppm_para((uint32_t)idx, nid,
            phy_multi_sync_get_record_ppm(status_ctxt, idx)
            >> PLC_NTB_PPM_SHIFT);
    }
    return ret;
#endif
    (void)status_ctxt;
    (void)nid;
    return 0;
}

#endif