/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/

#include "os_types.h"
#include "iot_img_hdr.h"
#include "os_mem.h"
#include "iot_wdg.h"
#include "iot_io.h"
#include "dbg_io.h"

#include "clk.h"
#include "ahb.h"
#include "ddrc.h"
#include "flash.h"
#include "ana.h"

#define APP_RAM_ADDR   0x0ffe0000
#define APP_FLASH_ADDR 0x1c008000

#define REG32(a)        (*((volatile uint32_t *)(a)))
//#define SP_DEBUG_UART_PORT 3

static int app_image_copy( )
{
    uint8_t *dst= (uint8_t*)APP_RAM_ADDR;
    uint8_t *src = (uint8_t*)APP_FLASH_ADDR;
    static char block[64];
    imgHdr hdr = {0};

    os_mem_cpy(block, src, sizeof(imgHdr));

    img_header_construct(&hdr, block);

    os_mem_cpy(dst, src + sizeof(imgHdr), iot_imghdr_get_imgSize(&hdr));

    return 0;
}

static int app_core_start()
{
    ahb_core0_set_start(APP_RAM_ADDR);

    ahb_core0_enable();

    ahb_core0_reset();

    return 0;
}

void sp_boot_hw_init()
{
    //disable auto-baud;
    REG32(0x44001020) &= ~0x1;
    REG32(0x50000008) |= 0x80;

    //change CPU core to 150M.
    clk_core_freq_set(CPU_FREQ_150M);

    //uart init;
    //dbg_uart_init_port(3, 1);

    //flash init;
    flash_init(1);

    // disable cache
    ahb_cache_disable();
#if RUN_IN_PSRAM
    //ddr init;
    ddr_cache_init();
#else
    ahb_set_cache_buffer_mode();
#endif
    // enable ahb cache
    ahb_cache_enable();
    //ahb_cache_reset();

#if RUN_IN_PSRAM
    //enable dmc cache;
    ahb_dmc_cache_enable();
#endif
     //cache space init;
    ahb_cache_fill_valid_space();
}

void sp_boot_load_sbl()
{
    app_image_copy();

    app_core_start();
}

void sp_boot_main_loop()
{
    //disable cpu1's wdt;
    wdg_deinit(HAL_WDG_CPU_1);

    while(1){
        __asm volatile ("nop");
    }
}