/**************************************************************************** Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED. This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT be copied by any method or incorporated into another program without the express written consent of Aerospace C.Power. This Information or any portion thereof remains the property of Aerospace C.Power. The Information contained herein is believed to be accurate and Aerospace C.Power assumes no responsibility or liability for its use in any way and conveys no license or title under any patent or copyright and makes no representation or warranty that this Information is free from patent or copyright infringement. ****************************************************************************/ #include "chip_reg_base.h" #include "hw_reg_api.h" #include "iot_bitops.h" #include "os_lock.h" #include "os_utils.h" #include "iot_config.h" #include "ahb_rf.h" #include "sram.h" #include "ahb.h" #include "flash.h" #include "sfc.h" #include "sec_glb.h" #if HW_PLATFORM > HW_PLATFORM_SIMU #include "dbg_io.h" #endif #include "iot_io.h" void cache_rst() { sec_glb_enable(SEC_GLB_EMC); ahb_cache_disable(); flash_init(1); ahb_cache_enable(); ahb_cache_reset(); } void cache_write_read_all() { int i = 0, j = 0, k = 0; uint32_t wdata[0x40] = {0}; uint32_t tmp; int len = 0x40; int offset = 0; int atom = 0x10; //int atom = 0x4000; // 16KB int times = 0x1FFF; // write cache uint32_t *dcache = (uint32_t *) 0x03000000; uint32_t *rcache = (uint32_t *) 0x03000000; for( j = 0; j < times; j++) { // write cache for ( i = 0; i < len; i++ ) { wdata[i] = i; *(dcache+offset+i) = wdata[i]; for(k=0; k< 100; k++); } // read dcache for ( i = 0; i < len; i++ ) { tmp = *(rcache+offset+i); if ( tmp != wdata[i] ) { iot_printf("dcache not equal \r\n"); iot_printf(" j : %d, i : %d\r\n", j, i); iot_printf("addr: %08x read: %08x, write: %08x\r\n", 0x13000000+i*4+j, tmp, wdata[i]); return ; } for(k=0; k< 100; k++); } offset += atom; } } void cache_write_read() { int i = 0, j = 0, k = 0; uint32_t wdata[0x50][0x10] = {0}; int len = 0x10; int offset = 0; int atom = 0x4000; // 16KB uint32_t tmp; uint32_t ran_pos = 0; uint32_t *dcache = (uint32_t *) 0x13000000; uint32_t *rcache = (uint32_t *) 0x13000000; iot_printf("write and read loop test\n"); for( j = 0; j < 0x50; j++) { // write cache for ( i = 0; i < len; i++ ) { wdata[j][i] = 1; *(dcache+offset+i*4) = wdata[j][i]; for(k=0; k< 300; k++); } for ( i = 0; i < len; i++ ) { tmp = *(rcache+offset+i*4 + ran_pos); if ( tmp != wdata[j][i] ) { iot_printf(" not equal \r\n"); iot_printf(" j : %d, i : %d\r\n", j, i); iot_printf("addr: %08x read: %08x, write: %08x\r\n", 0x13000000+i*4+j, tmp, wdata[j][i]); return ; } for(k=0; k< 300; k++); } offset += atom; } } void cache_write_read_byte() { uint8_t *code = (uint8_t *) 0x13000000; uint8_t *data = (uint8_t *) 0x13020000; uint8_t tmp = 0; int i = 0, j = 0; iot_printf("byte write and read test\n"); iot_printf("range of 0x13000000 - 0x13060000\n"); iot_printf("write code to 5a\r\n"); for (i = 0; i < 0x20000; i++) { *(code+i) = 0x5a; for(j = 0; j < 100; j++); if ( i % 0x100 == 0 ) { iot_printf("i: %08x\r\n", i); } } iot_printf("write code to a5\r\n"); for (i = 0; i < 0x40000; i++) { *(data+i) = 0x11; for(j = 0; j < 100; j++); if ( i % 0x100 == 0 ) { iot_printf("i: %08x\r\n", i); } } // read for (i = 0; i < 0x20000; i++) { tmp = *(code+i); if ( tmp != 0x5a ) { iot_printf("error: i: %08x\r\n", i); return ; } if ( i % 0x100 == 0 ) { iot_printf("read: %08x\r\n", i); } } for (i = 0; i < 0x40000; i++) { tmp = *(data+i); if ( tmp != 0x11 ) { iot_printf("error: i: %08x\r\n", i); return ; } if ( i % 0x100 == 0 ) { iot_printf("read: %08x\r\n", i); } } } void cache_test(){ dbg_uart_init(); /* rst sfc */ cache_rst(); cache_write_read_byte(); cache_write_read(); cache_write_read_all(); iot_printf("end............\n"); while(1); } #ifdef __GNUC__ int main(void) { cache_test(); return 0; } #endif // __GCC__