#ifndef CHIP_IRQ_VECTOR_H
#define CHIP_IRQ_VECTOR_H

enum CHIP_IRQ_VECTOR {
    GTMER0_INT                     = 0,
    GPIO_INT0                      = 1,
    UART0_INT                      = 2,
    UART1_INT                      = 3,
    UART2_INT                      = 4,
    UART3_INT                      = 5,
    GTMER1_INT                     = 6,
    RFPLC_INT0_COMMON_IRQ          = 7,
    RFPLC_INT1_COMMON_IRQ          = 8,
    GPIO_INT1                      = 9,
    PHY_INT_0                      = 10,
    PHY_INT_1                      = 11,
    PHY_INT_2                      = 12,
    PHY_INT_3                      = 13,
    PHY_INT_4                      = 14,
    SPI_S0_INT                     = 15,
    DMA0_INT3                      = 16,
    DMA0_INT2                      = 17,
    DMA0_INT1                      = 18,
    DMA0_INT0                      = 19,
    LEDC_INT                       = 20,
    MAC_INT_0                      = 21,
    MAC_INT_1                      = 22,
    MAC_INT_2                      = 23,
    MAC_INT_3                      = 24,
    SPI_M0_INT                     = 25,
    I2C_M1_INT                     = 26,
    I2C_M0_INT                     = 27,
    WDG1_INT                       = 28,
    WDG1_TIMEOUT_INT               = 29,
    WDG0_INT                       = 30,
    WDG0_TIMEOUT_INT               = 31,
    SFC_DONE_INT                   = 32,
    ADA_INT                        = 33,
    PWM0_INT                       = 34,
    PWM1_INT                       = 35,
    PWM2_INT                       = 36,
    PWM3_INT                       = 37,
    UART7_INT                      = 38,
    UART6_INT                      = 39,
    UART5_INT                      = 40,
    UART4_INT                      = 41,
    RFPLC_INT1_COMMON_SHARE_IRQ    = 42,
    RFPLC_INT1_COMMON_TIMEOUT      = 43,
    RFPLC_INT0_COMMON_SHARE_IRQ    = 44,
    RFPLC_INT0_COMMON_TIMEOUT      = 45,
    DMA1_INT3                      = 46,
    DMA1_INT2                      = 47,
    DMA1_INT1                      = 48,
    DMA1_INT0                      = 49,
    WDG2_INT                       = 50,
    WDG2_TIMEOUT_INT               = 51,
    SPI_M3_INT                     = 52,
    SPI_M2_INT                     = 53,
    SPI_M1_INT                     = 54,
    GTMR2_INT                      = 55,
    I2C_M2_INT                     = 56,
    MAILBOX0_INT                   = 57,
    MAILBOX1_INT                   = 58,
    MAILBOX2_INT                   = 59,
    MAILBOX3_INT                   = 60,
    MAILBOX4_INT                   = 61,
    MAILBOX5_INT                   = 62,
    SEC0_INT                       = 63,
    SEC1_INT                       = 64,
    I2C_M3_INT                     = 65,
    GMAC_SBD_INT                   = 66,
    USB_OTG_INT                    = 67,
    DMA2_INT3                      = 68,
    DMA2_INT2                      = 69,
    DMA2_INT1                      = 70,
    DMA2_INT0                      = 71,
    FFT_INT                        = 72,
    RTC_TMR_INT1                   = 73,
    RTC_TMR_INT0                   = 74,
    PWM4_INT                       = 75,
    PWM5_INT                       = 76,
    LEDC_FREE_INT                  = 77,
    GPIO_INT2                      = 78,
    SADC_REG_INT                   = 79,
    TPID_REG_INT                   = 80,

    CHIP_IRQ_VECTOR_MAX,
};

#endif