//----------------------------------- #define CFG_DMA_SW_CFG0_ADDR 0x0 #define DMA_SW_RX_ARBIT_INIT_OFFSET 3 #define DMA_SW_RX_ARBIT_INIT_MASK 0x00000008 #define DMA_SW_TX_ARBIT_INIT_OFFSET 2 #define DMA_SW_TX_ARBIT_INIT_MASK 0x00000004 #define DMA_SW_TX_SOFT_RST_OFFSET 1 #define DMA_SW_TX_SOFT_RST_MASK 0x00000002 #define DMA_SW_RX_SOFT_RST_OFFSET 0 #define DMA_SW_RX_SOFT_RST_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CRC0_CFG0_ADDR 0x4 #define CRC0_OUT_DONE_OFFSET 12 #define CRC0_OUT_DONE_MASK 0x00001000 #define CRC0_MODE_OFFSET 4 #define CRC0_MODE_MASK 0x00000FF0 #define CRC0_INIT_OFFSET 3 #define CRC0_INIT_MASK 0x00000008 #define CRC0_CHN_ID_OFFSET 1 #define CRC0_CHN_ID_MASK 0x00000006 #define CRC0_EB_OFFSET 0 #define CRC0_EB_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CRC0_CFG1_ADDR 0x8 #define CRC0_OUT_OFFSET 0 #define CRC0_OUT_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CRC0_CFG2_ADDR 0xC #define CRC0_POLYNOMIAL_OFFSET 0 #define CRC0_POLYNOMIAL_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CRC1_CFG0_ADDR 0x10 #define CRC1_OUT_DONE_OFFSET 12 #define CRC1_OUT_DONE_MASK 0x00001000 #define CRC1_MODE_OFFSET 4 #define CRC1_MODE_MASK 0x00000FF0 #define CRC1_INIT_OFFSET 3 #define CRC1_INIT_MASK 0x00000008 #define CRC1_CHN_ID_OFFSET 1 #define CRC1_CHN_ID_MASK 0x00000006 #define CRC1_EB_OFFSET 0 #define CRC1_EB_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CRC1_CFG1_ADDR 0x14 #define CRC1_OUT_OFFSET 0 #define CRC1_OUT_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CRC1_CFG2_ADDR 0x18 #define CRC1_POLYNOMIAL_OFFSET 0 #define CRC1_POLYNOMIAL_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CKSUM0_ADDR 0x1C #define CKSUM0_OUT_OFFSET 16 #define CKSUM0_OUT_MASK 0xFFFF0000 #define CKSUM0_INIT_OFFSET 3 #define CKSUM0_INIT_MASK 0x00000008 #define CKSUM0_ID_OFFSET 1 #define CKSUM0_ID_MASK 0x00000006 #define CKSUM0_EB_OFFSET 0 #define CKSUM0_EB_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CKSUM1_ADDR 0x20 #define CKSUM1_OUT_OFFSET 16 #define CKSUM1_OUT_MASK 0xFFFF0000 #define CKSUM1_INIT_OFFSET 3 #define CKSUM1_INIT_MASK 0x00000008 #define CKSUM1_ID_OFFSET 1 #define CKSUM1_ID_MASK 0x00000006 #define CKSUM1_EB_OFFSET 0 #define CKSUM1_EB_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_FP_CFG0_ADDR 0x24 #define DMA_SW_FP_INIT_OFFSET 31 #define DMA_SW_FP_INIT_MASK 0x80000000 #define DMA_SW_FP_RND_OFFSET 3 #define DMA_SW_FP_RND_MASK 0x00000038 #define DMA_SW_FP_MAX_MIN_CTRL_OFFSET 2 #define DMA_SW_FP_MAX_MIN_CTRL_MASK 0x00000004 #define DMA_SW_FP_FAC_CTRL_OFFSET 0 #define DMA_SW_FP_FAC_CTRL_MASK 0x00000003 //----------------------------------- #define CFG_DMA_SW_FP_CFG1_ADDR 0x28 #define DMA_SW_FP_FAC_OFFSET 0 #define DMA_SW_FP_FAC_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CHN0_FP_ST0_ADDR 0x2C #define DMA_SW_CHN0_FP_SUM_OFFSET 0 #define DMA_SW_CHN0_FP_SUM_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CHN0_FP_ST1_ADDR 0x30 #define DMA_SW_CHN0_FP_MAX_MIN_OFFSET 0 #define DMA_SW_CHN0_FP_MAX_MIN_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CHN1_FP_ST0_ADDR 0x34 #define DMA_SW_CHN1_FP_SUM_OFFSET 0 #define DMA_SW_CHN1_FP_SUM_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CHN1_FP_ST1_ADDR 0x38 #define DMA_SW_CHN1_FP_MAX_MIN_OFFSET 0 #define DMA_SW_CHN1_FP_MAX_MIN_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CHN2_FP_ST0_ADDR 0x3C #define DMA_SW_CHN2_FP_SUM_OFFSET 0 #define DMA_SW_CHN2_FP_SUM_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CHN2_FP_ST1_ADDR 0x40 #define DMA_SW_CHN2_FP_MAX_MIN_OFFSET 0 #define DMA_SW_CHN2_FP_MAX_MIN_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CHN3_FP_ST0_ADDR 0x44 #define DMA_SW_CHN3_FP_SUM_OFFSET 0 #define DMA_SW_CHN3_FP_SUM_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CHN3_FP_ST1_ADDR 0x48 #define DMA_SW_CHN3_FP_MAX_MIN_OFFSET 0 #define DMA_SW_CHN3_FP_MAX_MIN_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_FP_CHN0_INDEX_ADDR 0x50 #define DMA_SW_CHN0_FP_INDEX_OFFSET 0 #define DMA_SW_CHN0_FP_INDEX_MASK 0x0000FFFF //----------------------------------- #define CFG_DMA_SW_FP_CHN1_INDEX_ADDR 0x54 #define DMA_SW_CHN1_FP_INDEX_OFFSET 0 #define DMA_SW_CHN1_FP_INDEX_MASK 0x0000FFFF //----------------------------------- #define CFG_DMA_SW_FP_CHN2_INDEX_ADDR 0x58 #define DMA_SW_CHN2_FP_INDEX_OFFSET 0 #define DMA_SW_CHN2_FP_INDEX_MASK 0x0000FFFF //----------------------------------- #define CFG_DMA_SW_FP_CHN3_INDEX_ADDR 0x5C #define DMA_SW_CHN3_FP_INDEX_OFFSET 0 #define DMA_SW_CHN3_FP_INDEX_MASK 0x0000FFFF //----------------------------------- #define CFG_DMA_SW_RX_INT_STATUS_ADDR 0x7C #define DMA_SW_RX_INT_ST_OFFSET 0 #define DMA_SW_RX_INT_ST_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_TX_INT_STATUS_ADDR 0x80 #define DMA_SW_TX_INT_ST_OFFSET 0 #define DMA_SW_TX_INT_ST_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_RX_DBG_BUS0_ADDR 0x84 #define DMA_SW_RX_DBG_BUS0_OFFSET 0 #define DMA_SW_RX_DBG_BUS0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_RX_DBG_BUS1_ADDR 0x88 #define DMA_SW_RX_DBG_BUS1_OFFSET 0 #define DMA_SW_RX_DBG_BUS1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_RX_DBG_BUS2_ADDR 0x8C #define DMA_SW_RX_DBG_BUS2_OFFSET 0 #define DMA_SW_RX_DBG_BUS2_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_TX_DBG_BUS0_ADDR 0x90 #define DMA_SW_TX_DBG_BUS0_OFFSET 0 #define DMA_SW_TX_DBG_BUS0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_TX_DBG_BUS1_ADDR 0x94 #define DMA_SW_TX_DBG_BUS1_OFFSET 0 #define DMA_SW_TX_DBG_BUS1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_SET_RX_LINKADDR_ADDR 0x98 #define DMA_SW_RX_SET_LINKADDR_OFFSET 0 #define DMA_SW_RX_SET_LINKADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_SET_TX_LINKADDR_ADDR 0x9C #define DMA_SW_TX_SET_LINKADDR_OFFSET 0 #define DMA_SW_TX_SET_LINKADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CHN0_CFG0_ADDR 0x100 #define CH0_RX_LINK_ADDR_OFFSET 0 #define CH0_RX_LINK_ADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CHN0_CFG1_ADDR 0x104 #define CH0_TX_LINK_ADDR_OFFSET 0 #define CH0_TX_LINK_ADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CHN0_CFG2_ADDR 0x108 #define CH0_RX_BIT_ORDER_SEL_OFFSET 23 #define CH0_RX_BIT_ORDER_SEL_MASK 0x00800000 #define CH0_RX_BYTE_ORDER_SEL_OFFSET 22 #define CH0_RX_BYTE_ORDER_SEL_MASK 0x00400000 #define CH0_TX_BIT_ORDER_SEL_OFFSET 21 #define CH0_TX_BIT_ORDER_SEL_MASK 0x00200000 #define CH0_TX_BYTE_ORDER_SEL_OFFSET 20 #define CH0_TX_BYTE_ORDER_SEL_MASK 0x00100000 #define CH0_DECR_RX_EXCEED_TX_LEN_EN_OFFSET 16 #define CH0_DECR_RX_EXCEED_TX_LEN_EN_MASK 0x00010000 #define CH0_DECR_TX_EXCEED_RX_LEN_EN_OFFSET 15 #define CH0_DECR_TX_EXCEED_RX_LEN_EN_MASK 0x00008000 #define CH0_TX_AHB_STEP_SIZE_OFFSET 12 #define CH0_TX_AHB_STEP_SIZE_MASK 0x00007000 #define CH0_RX_AHB_STEP_SIZE_OFFSET 9 #define CH0_RX_AHB_STEP_SIZE_MASK 0x00000E00 #define CH0_WEIGHT_OFFSET 5 #define CH0_WEIGHT_MASK 0x000001E0 #define CH0_STOP_OFFSET 4 #define CH0_STOP_MASK 0x00000010 #define CH0_RESTART_OFFSET 3 #define CH0_RESTART_MASK 0x00000008 #define CH0_START_OFFSET 2 #define CH0_START_MASK 0x00000004 #define CH0_PRIORITY_OFFSET 0 #define CH0_PRIORITY_MASK 0x00000003 //----------------------------------- #define CFG_DMA_SW_CHN0_INTR_RAW_ADDR 0x10C #define CH0_DECR_RX_EXCEED_TX_LEN_RAW_OFFSET 6 #define CH0_DECR_RX_EXCEED_TX_LEN_RAW_MASK 0x00000040 #define CH0_DECR_TX_EXCEED_RX_LEN_RAW_OFFSET 5 #define CH0_DECR_TX_EXCEED_RX_LEN_RAW_MASK 0x00000020 #define CH0_TX_LINKADDR_IS_EMP_RAW_OFFSET 4 #define CH0_TX_LINKADDR_IS_EMP_RAW_MASK 0x00000010 #define CH0_TX_ALL_DECR_INT_RAW_OFFSET 3 #define CH0_TX_ALL_DECR_INT_RAW_MASK 0x00000008 #define CH0_TX_CURR_DECR_INT_RAW_OFFSET 2 #define CH0_TX_CURR_DECR_INT_RAW_MASK 0x00000004 #define CH0_RX_ALL_DECR_INT_RAW_OFFSET 1 #define CH0_RX_ALL_DECR_INT_RAW_MASK 0x00000002 #define CH0_RX_CURR_DECR_INT_RAW_OFFSET 0 #define CH0_RX_CURR_DECR_INT_RAW_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CHN0_INTR_ST_ADDR 0x110 #define CH0_DECR_RX_EXCEED_TX_LEN_ST_OFFSET 6 #define CH0_DECR_RX_EXCEED_TX_LEN_ST_MASK 0x00000040 #define CH0_DECR_TX_EXCEED_RX_LEN_ST_OFFSET 5 #define CH0_DECR_TX_EXCEED_RX_LEN_ST_MASK 0x00000020 #define CH0_TX_LINKADDR_IS_EMP_ST_OFFSET 4 #define CH0_TX_LINKADDR_IS_EMP_ST_MASK 0x00000010 #define CH0_TX_ALL_DECR_INT_ST_OFFSET 3 #define CH0_TX_ALL_DECR_INT_ST_MASK 0x00000008 #define CH0_TX_CURR_DECR_INT_ST_OFFSET 2 #define CH0_TX_CURR_DECR_INT_ST_MASK 0x00000004 #define CH0_RX_ALL_DECR_INT_ST_OFFSET 1 #define CH0_RX_ALL_DECR_INT_ST_MASK 0x00000002 #define CH0_RX_CURR_DECR_INT_ST_OFFSET 0 #define CH0_RX_CURR_DECR_INT_ST_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CHN0_INTR_ENA_ADDR 0x114 #define CH0_DECR_RX_EXCEED_TX_LEN_ENA_OFFSET 6 #define CH0_DECR_RX_EXCEED_TX_LEN_ENA_MASK 0x00000040 #define CH0_DECR_TX_EXCEED_RX_LEN_ENA_OFFSET 5 #define CH0_DECR_TX_EXCEED_RX_LEN_ENA_MASK 0x00000020 #define CH0_TX_LINKADDR_IS_EMP_ENA_OFFSET 4 #define CH0_TX_LINKADDR_IS_EMP_ENA_MASK 0x00000010 #define CH0_TX_ALL_DECR_INT_ENA_OFFSET 3 #define CH0_TX_ALL_DECR_INT_ENA_MASK 0x00000008 #define CH0_TX_CURR_DECR_INT_ENA_OFFSET 2 #define CH0_TX_CURR_DECR_INT_ENA_MASK 0x00000004 #define CH0_RX_ALL_DECR_INT_ENA_OFFSET 1 #define CH0_RX_ALL_DECR_INT_ENA_MASK 0x00000002 #define CH0_RX_CURR_DECR_INT_ENA_OFFSET 0 #define CH0_RX_CURR_DECR_INT_ENA_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CHN0_INTR_CLR_ADDR 0x118 #define CH0_DECR_RX_EXCEED_TX_LEN_CLR_OFFSET 6 #define CH0_DECR_RX_EXCEED_TX_LEN_CLR_MASK 0x00000040 #define CH0_DECR_TX_EXCEED_RX_LEN_CLR_OFFSET 5 #define CH0_DECR_TX_EXCEED_RX_LEN_CLR_MASK 0x00000020 #define CH0_TX_LINKADDR_IS_EMP_CLR_OFFSET 4 #define CH0_TX_LINKADDR_IS_EMP_CLR_MASK 0x00000010 #define CH0_TX_ALL_DECR_INT_CLR_OFFSET 3 #define CH0_TX_ALL_DECR_INT_CLR_MASK 0x00000008 #define CH0_TX_CURR_DECR_INT_CLR_OFFSET 2 #define CH0_TX_CURR_DECR_INT_CLR_MASK 0x00000004 #define CH0_RX_ALL_DECR_INT_CLR_OFFSET 1 #define CH0_RX_ALL_DECR_INT_CLR_MASK 0x00000002 #define CH0_RX_CURR_DECR_INT_CLR_OFFSET 0 #define CH0_RX_CURR_DECR_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CHN1_CFG0_ADDR 0x120 #define CH1_RX_LINK_ADDR_OFFSET 0 #define CH1_RX_LINK_ADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CHN1_CFG1_ADDR 0x124 #define CH1_TX_LINK_ADDR_OFFSET 0 #define CH1_TX_LINK_ADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CHN1_CFG2_ADDR 0x128 #define CH1_RX_BIT_ORDER_SEL_OFFSET 23 #define CH1_RX_BIT_ORDER_SEL_MASK 0x00800000 #define CH1_RX_BYTE_ORDER_SEL_OFFSET 22 #define CH1_RX_BYTE_ORDER_SEL_MASK 0x00400000 #define CH1_TX_BIT_ORDER_SEL_OFFSET 21 #define CH1_TX_BIT_ORDER_SEL_MASK 0x00200000 #define CH1_TX_BYTE_ORDER_SEL_OFFSET 20 #define CH1_TX_BYTE_ORDER_SEL_MASK 0x00100000 #define CH1_DECR_RX_EXCEED_TX_LEN_EN_OFFSET 16 #define CH1_DECR_RX_EXCEED_TX_LEN_EN_MASK 0x00010000 #define CH1_DECR_TX_EXCEED_RX_LEN_EN_OFFSET 15 #define CH1_DECR_TX_EXCEED_RX_LEN_EN_MASK 0x00008000 #define CH1_TX_AHB_STEP_SIZE_OFFSET 12 #define CH1_TX_AHB_STEP_SIZE_MASK 0x00007000 #define CH1_RX_AHB_STEP_SIZE_OFFSET 9 #define CH1_RX_AHB_STEP_SIZE_MASK 0x00000E00 #define CH1_WEIGHT_OFFSET 5 #define CH1_WEIGHT_MASK 0x000001E0 #define CH1_STOP_OFFSET 4 #define CH1_STOP_MASK 0x00000010 #define CH1_RESTART_OFFSET 3 #define CH1_RESTART_MASK 0x00000008 #define CH1_START_OFFSET 2 #define CH1_START_MASK 0x00000004 #define CH1_PRIORITY_OFFSET 0 #define CH1_PRIORITY_MASK 0x00000003 //----------------------------------- #define CFG_DMA_SW_CHN1_INTR_RAW_ADDR 0x12C #define CH1_DECR_RX_EXCEED_TX_LEN_RAW_OFFSET 6 #define CH1_DECR_RX_EXCEED_TX_LEN_RAW_MASK 0x00000040 #define CH1_DECR_TX_EXCEED_RX_LEN_RAW_OFFSET 5 #define CH1_DECR_TX_EXCEED_RX_LEN_RAW_MASK 0x00000020 #define CH1_TX_LINKADDR_IS_EMP_RAW_OFFSET 4 #define CH1_TX_LINKADDR_IS_EMP_RAW_MASK 0x00000010 #define CH1_TX_ALL_DECR_INT_RAW_OFFSET 3 #define CH1_TX_ALL_DECR_INT_RAW_MASK 0x00000008 #define CH1_TX_CURR_DECR_INT_RAW_OFFSET 2 #define CH1_TX_CURR_DECR_INT_RAW_MASK 0x00000004 #define CH1_RX_ALL_DECR_INT_RAW_OFFSET 1 #define CH1_RX_ALL_DECR_INT_RAW_MASK 0x00000002 #define CH1_RX_CURR_DECR_INT_RAW_OFFSET 0 #define CH1_RX_CURR_DECR_INT_RAW_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CHN1_INTR_ST_ADDR 0x130 #define CH1_DECR_RX_EXCEED_TX_LEN_ST_OFFSET 6 #define CH1_DECR_RX_EXCEED_TX_LEN_ST_MASK 0x00000040 #define CH1_DECR_TX_EXCEED_RX_LEN_ST_OFFSET 5 #define CH1_DECR_TX_EXCEED_RX_LEN_ST_MASK 0x00000020 #define CH1_TX_LINKADDR_IS_EMP_ST_OFFSET 4 #define CH1_TX_LINKADDR_IS_EMP_ST_MASK 0x00000010 #define CH1_TX_ALL_DECR_INT_ST_OFFSET 3 #define CH1_TX_ALL_DECR_INT_ST_MASK 0x00000008 #define CH1_TX_CURR_DECR_INT_ST_OFFSET 2 #define CH1_TX_CURR_DECR_INT_ST_MASK 0x00000004 #define CH1_RX_ALL_DECR_INT_ST_OFFSET 1 #define CH1_RX_ALL_DECR_INT_ST_MASK 0x00000002 #define CH1_RX_CURR_DECR_INT_ST_OFFSET 0 #define CH1_RX_CURR_DECR_INT_ST_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CHN1_INTR_ENA_ADDR 0x134 #define CH1_DECR_RX_EXCEED_TX_LEN_ENA_OFFSET 6 #define CH1_DECR_RX_EXCEED_TX_LEN_ENA_MASK 0x00000040 #define CH1_DECR_TX_EXCEED_RX_LEN_ENA_OFFSET 5 #define CH1_DECR_TX_EXCEED_RX_LEN_ENA_MASK 0x00000020 #define CH1_TX_LINKADDR_IS_EMP_ENA_OFFSET 4 #define CH1_TX_LINKADDR_IS_EMP_ENA_MASK 0x00000010 #define CH1_TX_ALL_DECR_INT_ENA_OFFSET 3 #define CH1_TX_ALL_DECR_INT_ENA_MASK 0x00000008 #define CH1_TX_CURR_DECR_INT_ENA_OFFSET 2 #define CH1_TX_CURR_DECR_INT_ENA_MASK 0x00000004 #define CH1_RX_ALL_DECR_INT_ENA_OFFSET 1 #define CH1_RX_ALL_DECR_INT_ENA_MASK 0x00000002 #define CH1_RX_CURR_DECR_INT_ENA_OFFSET 0 #define CH1_RX_CURR_DECR_INT_ENA_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CHN1_INTR_CLR_ADDR 0x138 #define CH1_DECR_RX_EXCEED_TX_LEN_CLR_OFFSET 6 #define CH1_DECR_RX_EXCEED_TX_LEN_CLR_MASK 0x00000040 #define CH1_DECR_TX_EXCEED_RX_LEN_CLR_OFFSET 5 #define CH1_DECR_TX_EXCEED_RX_LEN_CLR_MASK 0x00000020 #define CH1_TX_LINKADDR_IS_EMP_CLR_OFFSET 4 #define CH1_TX_LINKADDR_IS_EMP_CLR_MASK 0x00000010 #define CH1_TX_ALL_DECR_INT_CLR_OFFSET 3 #define CH1_TX_ALL_DECR_INT_CLR_MASK 0x00000008 #define CH1_TX_CURR_DECR_INT_CLR_OFFSET 2 #define CH1_TX_CURR_DECR_INT_CLR_MASK 0x00000004 #define CH1_RX_ALL_DECR_INT_CLR_OFFSET 1 #define CH1_RX_ALL_DECR_INT_CLR_MASK 0x00000002 #define CH1_RX_CURR_DECR_INT_CLR_OFFSET 0 #define CH1_RX_CURR_DECR_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CHN2_CFG0_ADDR 0x140 #define CH2_RX_LINK_ADDR_OFFSET 0 #define CH2_RX_LINK_ADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CHN2_CFG1_ADDR 0x144 #define CH2_TX_LINK_ADDR_OFFSET 0 #define CH2_TX_LINK_ADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CHN2_CFG2_ADDR 0x148 #define CH2_RX_BIT_ORDER_SEL_OFFSET 23 #define CH2_RX_BIT_ORDER_SEL_MASK 0x00800000 #define CH2_RX_BYTE_ORDER_SEL_OFFSET 22 #define CH2_RX_BYTE_ORDER_SEL_MASK 0x00400000 #define CH2_TX_BIT_ORDER_SEL_OFFSET 21 #define CH2_TX_BIT_ORDER_SEL_MASK 0x00200000 #define CH2_TX_BYTE_ORDER_SEL_OFFSET 20 #define CH2_TX_BYTE_ORDER_SEL_MASK 0x00100000 #define CH2_DECR_RX_EXCEED_TX_LEN_EN_OFFSET 16 #define CH2_DECR_RX_EXCEED_TX_LEN_EN_MASK 0x00010000 #define CH2_DECR_TX_EXCEED_RX_LEN_EN_OFFSET 15 #define CH2_DECR_TX_EXCEED_RX_LEN_EN_MASK 0x00008000 #define CH2_TX_AHB_STEP_SIZE_OFFSET 12 #define CH2_TX_AHB_STEP_SIZE_MASK 0x00007000 #define CH2_RX_AHB_STEP_SIZE_OFFSET 9 #define CH2_RX_AHB_STEP_SIZE_MASK 0x00000E00 #define CH2_WEIGHT_OFFSET 5 #define CH2_WEIGHT_MASK 0x000001E0 #define CH2_STOP_OFFSET 4 #define CH2_STOP_MASK 0x00000010 #define CH2_RESTART_OFFSET 3 #define CH2_RESTART_MASK 0x00000008 #define CH2_START_OFFSET 2 #define CH2_START_MASK 0x00000004 #define CH2_PRIORITY_OFFSET 0 #define CH2_PRIORITY_MASK 0x00000003 //----------------------------------- #define CFG_DMA_SW_CHN2_INTR_RAW_ADDR 0x14C #define CH2_DECR_RX_EXCEED_TX_LEN_RAW_OFFSET 6 #define CH2_DECR_RX_EXCEED_TX_LEN_RAW_MASK 0x00000040 #define CH2_DECR_TX_EXCEED_RX_LEN_RAW_OFFSET 5 #define CH2_DECR_TX_EXCEED_RX_LEN_RAW_MASK 0x00000020 #define CH2_TX_LINKADDR_IS_EMP_RAW_OFFSET 4 #define CH2_TX_LINKADDR_IS_EMP_RAW_MASK 0x00000010 #define CH2_TX_ALL_DECR_INT_RAW_OFFSET 3 #define CH2_TX_ALL_DECR_INT_RAW_MASK 0x00000008 #define CH2_TX_CURR_DECR_INT_RAW_OFFSET 2 #define CH2_TX_CURR_DECR_INT_RAW_MASK 0x00000004 #define CH2_RX_ALL_DECR_INT_RAW_OFFSET 1 #define CH2_RX_ALL_DECR_INT_RAW_MASK 0x00000002 #define CH2_RX_CURR_DECR_INT_RAW_OFFSET 0 #define CH2_RX_CURR_DECR_INT_RAW_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CHN2_INTR_ST_ADDR 0x150 #define CH2_DECR_RX_EXCEED_TX_LEN_ST_OFFSET 6 #define CH2_DECR_RX_EXCEED_TX_LEN_ST_MASK 0x00000040 #define CH2_DECR_TX_EXCEED_RX_LEN_ST_OFFSET 5 #define CH2_DECR_TX_EXCEED_RX_LEN_ST_MASK 0x00000020 #define CH2_TX_LINKADDR_IS_EMP_ST_OFFSET 4 #define CH2_TX_LINKADDR_IS_EMP_ST_MASK 0x00000010 #define CH2_TX_ALL_DECR_INT_ST_OFFSET 3 #define CH2_TX_ALL_DECR_INT_ST_MASK 0x00000008 #define CH2_TX_CURR_DECR_INT_ST_OFFSET 2 #define CH2_TX_CURR_DECR_INT_ST_MASK 0x00000004 #define CH2_RX_ALL_DECR_INT_ST_OFFSET 1 #define CH2_RX_ALL_DECR_INT_ST_MASK 0x00000002 #define CH2_RX_CURR_DECR_INT_ST_OFFSET 0 #define CH2_RX_CURR_DECR_INT_ST_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CHN2_INTR_ENA_ADDR 0x154 #define CH2_DECR_RX_EXCEED_TX_LEN_ENA_OFFSET 6 #define CH2_DECR_RX_EXCEED_TX_LEN_ENA_MASK 0x00000040 #define CH2_DECR_TX_EXCEED_RX_LEN_ENA_OFFSET 5 #define CH2_DECR_TX_EXCEED_RX_LEN_ENA_MASK 0x00000020 #define CH2_TX_LINKADDR_IS_EMP_ENA_OFFSET 4 #define CH2_TX_LINKADDR_IS_EMP_ENA_MASK 0x00000010 #define CH2_TX_ALL_DECR_INT_ENA_OFFSET 3 #define CH2_TX_ALL_DECR_INT_ENA_MASK 0x00000008 #define CH2_TX_CURR_DECR_INT_ENA_OFFSET 2 #define CH2_TX_CURR_DECR_INT_ENA_MASK 0x00000004 #define CH2_RX_ALL_DECR_INT_ENA_OFFSET 1 #define CH2_RX_ALL_DECR_INT_ENA_MASK 0x00000002 #define CH2_RX_CURR_DECR_INT_ENA_OFFSET 0 #define CH2_RX_CURR_DECR_INT_ENA_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CHN2_INTR_CLR_ADDR 0x158 #define CH2_DECR_RX_EXCEED_TX_LEN_CLR_OFFSET 6 #define CH2_DECR_RX_EXCEED_TX_LEN_CLR_MASK 0x00000040 #define CH2_DECR_TX_EXCEED_RX_LEN_CLR_OFFSET 5 #define CH2_DECR_TX_EXCEED_RX_LEN_CLR_MASK 0x00000020 #define CH2_TX_LINKADDR_IS_EMP_CLR_OFFSET 4 #define CH2_TX_LINKADDR_IS_EMP_CLR_MASK 0x00000010 #define CH2_TX_ALL_DECR_INT_CLR_OFFSET 3 #define CH2_TX_ALL_DECR_INT_CLR_MASK 0x00000008 #define CH2_TX_CURR_DECR_INT_CLR_OFFSET 2 #define CH2_TX_CURR_DECR_INT_CLR_MASK 0x00000004 #define CH2_RX_ALL_DECR_INT_CLR_OFFSET 1 #define CH2_RX_ALL_DECR_INT_CLR_MASK 0x00000002 #define CH2_RX_CURR_DECR_INT_CLR_OFFSET 0 #define CH2_RX_CURR_DECR_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CHN3_CFG0_ADDR 0x160 #define CH3_RX_LINK_ADDR_OFFSET 0 #define CH3_RX_LINK_ADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CHN3_CFG1_ADDR 0x164 #define CH3_TX_LINK_ADDR_OFFSET 0 #define CH3_TX_LINK_ADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMA_SW_CHN3_CFG2_ADDR 0x168 #define CH3_RX_BIT_ORDER_SEL_OFFSET 23 #define CH3_RX_BIT_ORDER_SEL_MASK 0x00800000 #define CH3_RX_BYTE_ORDER_SEL_OFFSET 22 #define CH3_RX_BYTE_ORDER_SEL_MASK 0x00400000 #define CH3_TX_BIT_ORDER_SEL_OFFSET 21 #define CH3_TX_BIT_ORDER_SEL_MASK 0x00200000 #define CH3_TX_BYTE_ORDER_SEL_OFFSET 20 #define CH3_TX_BYTE_ORDER_SEL_MASK 0x00100000 #define CH3_DECR_RX_EXCEED_TX_LEN_EN_OFFSET 16 #define CH3_DECR_RX_EXCEED_TX_LEN_EN_MASK 0x00010000 #define CH3_DECR_TX_EXCEED_RX_LEN_EN_OFFSET 15 #define CH3_DECR_TX_EXCEED_RX_LEN_EN_MASK 0x00008000 #define CH3_TX_AHB_STEP_SIZE_OFFSET 12 #define CH3_TX_AHB_STEP_SIZE_MASK 0x00007000 #define CH3_RX_AHB_STEP_SIZE_OFFSET 9 #define CH3_RX_AHB_STEP_SIZE_MASK 0x00000E00 #define CH3_WEIGHT_OFFSET 5 #define CH3_WEIGHT_MASK 0x000001E0 #define CH3_STOP_OFFSET 4 #define CH3_STOP_MASK 0x00000010 #define CH3_RESTART_OFFSET 3 #define CH3_RESTART_MASK 0x00000008 #define CH3_START_OFFSET 2 #define CH3_START_MASK 0x00000004 #define CH3_PRIORITY_OFFSET 0 #define CH3_PRIORITY_MASK 0x00000003 //----------------------------------- #define CFG_DMA_SW_CHN3_INTR_RAW_ADDR 0x16C #define CH3_DECR_RX_EXCEED_TX_LEN_RAW_OFFSET 6 #define CH3_DECR_RX_EXCEED_TX_LEN_RAW_MASK 0x00000040 #define CH3_DECR_TX_EXCEED_RX_LEN_RAW_OFFSET 5 #define CH3_DECR_TX_EXCEED_RX_LEN_RAW_MASK 0x00000020 #define CH3_TX_LINKADDR_IS_EMP_RAW_OFFSET 4 #define CH3_TX_LINKADDR_IS_EMP_RAW_MASK 0x00000010 #define CH3_TX_ALL_DECR_INT_RAW_OFFSET 3 #define CH3_TX_ALL_DECR_INT_RAW_MASK 0x00000008 #define CH3_TX_CURR_DECR_INT_RAW_OFFSET 2 #define CH3_TX_CURR_DECR_INT_RAW_MASK 0x00000004 #define CH3_RX_ALL_DECR_INT_RAW_OFFSET 1 #define CH3_RX_ALL_DECR_INT_RAW_MASK 0x00000002 #define CH3_RX_CURR_DECR_INT_RAW_OFFSET 0 #define CH3_RX_CURR_DECR_INT_RAW_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CHN3_INTR_ST_ADDR 0x170 #define CH3_DECR_RX_EXCEED_TX_LEN_ST_OFFSET 6 #define CH3_DECR_RX_EXCEED_TX_LEN_ST_MASK 0x00000040 #define CH3_DECR_TX_EXCEED_RX_LEN_ST_OFFSET 5 #define CH3_DECR_TX_EXCEED_RX_LEN_ST_MASK 0x00000020 #define CH3_TX_LINKADDR_IS_EMP_ST_OFFSET 4 #define CH3_TX_LINKADDR_IS_EMP_ST_MASK 0x00000010 #define CH3_TX_ALL_DECR_INT_ST_OFFSET 3 #define CH3_TX_ALL_DECR_INT_ST_MASK 0x00000008 #define CH3_TX_CURR_DECR_INT_ST_OFFSET 2 #define CH3_TX_CURR_DECR_INT_ST_MASK 0x00000004 #define CH3_RX_ALL_DECR_INT_ST_OFFSET 1 #define CH3_RX_ALL_DECR_INT_ST_MASK 0x00000002 #define CH3_RX_CURR_DECR_INT_ST_OFFSET 0 #define CH3_RX_CURR_DECR_INT_ST_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CHN3_INTR_ENA_ADDR 0x174 #define CH3_DECR_RX_EXCEED_TX_LEN_ENA_OFFSET 6 #define CH3_DECR_RX_EXCEED_TX_LEN_ENA_MASK 0x00000040 #define CH3_DECR_TX_EXCEED_RX_LEN_ENA_OFFSET 5 #define CH3_DECR_TX_EXCEED_RX_LEN_ENA_MASK 0x00000020 #define CH3_TX_LINKADDR_IS_EMP_ENA_OFFSET 4 #define CH3_TX_LINKADDR_IS_EMP_ENA_MASK 0x00000010 #define CH3_TX_ALL_DECR_INT_ENA_OFFSET 3 #define CH3_TX_ALL_DECR_INT_ENA_MASK 0x00000008 #define CH3_TX_CURR_DECR_INT_ENA_OFFSET 2 #define CH3_TX_CURR_DECR_INT_ENA_MASK 0x00000004 #define CH3_RX_ALL_DECR_INT_ENA_OFFSET 1 #define CH3_RX_ALL_DECR_INT_ENA_MASK 0x00000002 #define CH3_RX_CURR_DECR_INT_ENA_OFFSET 0 #define CH3_RX_CURR_DECR_INT_ENA_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SW_CHN3_INTR_CLR_ADDR 0x178 #define CH3_DECR_RX_EXCEED_TX_LEN_CLR_OFFSET 6 #define CH3_DECR_RX_EXCEED_TX_LEN_CLR_MASK 0x00000040 #define CH3_DECR_TX_EXCEED_RX_LEN_CLR_OFFSET 5 #define CH3_DECR_TX_EXCEED_RX_LEN_CLR_MASK 0x00000020 #define CH3_TX_LINKADDR_IS_EMP_CLR_OFFSET 4 #define CH3_TX_LINKADDR_IS_EMP_CLR_MASK 0x00000010 #define CH3_TX_ALL_DECR_INT_CLR_OFFSET 3 #define CH3_TX_ALL_DECR_INT_CLR_MASK 0x00000008 #define CH3_TX_CURR_DECR_INT_CLR_OFFSET 2 #define CH3_TX_CURR_DECR_INT_CLR_MASK 0x00000004 #define CH3_RX_ALL_DECR_INT_CLR_OFFSET 1 #define CH3_RX_ALL_DECR_INT_CLR_MASK 0x00000002 #define CH3_RX_CURR_DECR_INT_CLR_OFFSET 0 #define CH3_RX_CURR_DECR_INT_CLR_MASK 0x00000001 //HW module read/write macro #define DMA_SW_RF_READ_REG(addr) SOC_READ_REG(DMA_SW_RF_BASEADDR + addr) #define DMA_SW_RF_WRITE_REG(addr,value) SOC_WRITE_REG(DMA_SW_RF_BASEADDR + addr,value)