#include "os_types.h"
#include "os_mem.h"
#include "dbg_io.h"
#include "iot_diag.h"
#include "iot_io.h"
#include "ddr_reg_rf.h"
#include "dmc_reg_rf.h"
#include "hw_reg_api.h"
#include "ahb.h"

#if 0
#include "input.h"
#include "ref.h"
#endif
#include "ahb_rf.h"

#include "dvp_rf.h"
#include "k3d_reg.h"
#include "ai_glb_reg.h"

// ############################################################################
// common define
#define REG32(a)    (*((volatile uint32_t *)(a)))

// common define end
// ############################################################################

// ############################################################################
// ddr define
#define MODE_REGISTER_WRITE 0xc0
#define MODE_REGISTER_READ 0x40
#define DDR_BASE    0x55228000
#define DDR_POERATION_INT_MEM3_ADDR (DDR_BASE + 0x11c)
#define DDR_RST_CFG_ADDR (DDR_BASE + 0x4)

typedef enum ddr_dev_x8_x16_mode {
    DEV_X8_MODE = 0,
    DEV_X16_MODE = 1,
}ddr_dev_x8_x16_mode_t;
// ddr define end
// ############################################################################
// ############################################################################
// ai define
#define AI_INNER_RAM0_ADDR  0x73000000
#define AI_INNER_RAM1_ADDR  0x73020000

#define AI_INNER_RAM_START_ADDR 0x10000
#define AI_INNER_RAM_END_ADDR   0x12000

#define AI_DDR_START_ADDR   0x0

#define K3D_SUB_P 1

#define K3D_CACHE_PRIME_ADDR    0x20000000
#define DVP_CACHE_START0_ADDR   0x400000
#define DVP_CACHE_START3_ADDR   0x600000


enum {
    DVP_MODE_RAW = 0,
    DVP_MODE_BINA = 1,
} dvp_mode_t;

typedef struct _dvp_crop {
    uint8_t ena;
    uint16_t x0;
    uint16_t y0;
    uint16_t x1;
    uint16_t y1;
} dvp_crop_t;
typedef struct _dvp_reg_cfg {
    uint8_t mode;
    dvp_crop_t crop;
} dvp_reg_cfg_t;
// ############################################################################

void dvp_module_crop_cfg(dvp_crop_t *crop)
{
    uint32_t tmp;
    if (crop->ena) {
        tmp = DVP_RF0_READ_REG(CFG_CROP_CFG0_ADDR);
        REG_FIELD_SET(CROP_X0_SHD, tmp, crop->x0);
        REG_FIELD_SET(CROP_Y0_SHD, tmp, crop->y0);
        DVP_RF0_WRITE_REG(CFG_CROP_CFG0_ADDR, tmp);
        tmp = DVP_RF0_READ_REG(CFG_CROP_CFG1_ADDR);
        REG_FIELD_SET(CROP_X1_SHD, tmp, crop->x1);
        REG_FIELD_SET(CROP_Y1_SHD, tmp, crop->y1);
        DVP_RF0_WRITE_REG(CFG_CROP_CFG1_ADDR, tmp);

        tmp = DVP_RF0_READ_REG(CFG_DCAM_CTRL_ADDR);
        REG_FIELD_SET(CROP_EN_SHD, tmp, 1);     // crop enable
        DVP_RF0_WRITE_REG(CFG_BINA_AEC_ADDR, tmp);
    } else {
        tmp = DVP_RF0_READ_REG(CFG_DCAM_CTRL_ADDR);
        REG_FIELD_SET(CROP_EN_SHD, tmp, 0);     // crop enable
        DVP_RF0_WRITE_REG(CFG_BINA_AEC_ADDR, tmp);
    }
}

void dvp_module_cfg(dvp_reg_cfg_t *cfg)
{
    uint32_t tmp;

    // source config
    tmp = DVP_RF0_READ_REG(CFG_SOURCE_CFG_ADDR);
    REG_FIELD_SET(DTYPE, tmp, 0x4);
    REG_FIELD_SET(DVP_SLOW_MODE, tmp, 1);
    REG_FIELD_SET(DWIDTH, tmp, 0);
    REG_FIELD_SET(SOURCE_EDIAN, tmp, 1);
    REG_FIELD_SET(BIT_EDIAN, tmp, 1);
    REG_FIELD_SET(SRC_SEL, tmp, 1);
    REG_FIELD_SET(FRAME_SRC_MODE, tmp, 0);
    REG_FIELD_SET(CFG_BIN_RAM_FULL, tmp, 1);
    DVP_RF0_WRITE_REG(CFG_SOURCE_CFG_ADDR, tmp);

    // des cfg
    tmp = DVP_RF0_READ_REG(CFG_DES_CFG_ADDR);
    REG_FIELD_SET(DES_CFG_SHD, tmp, 0x1);   // 0: REGB888 1: Y 2: YUV422
    DVP_RF0_WRITE_REG(CFG_DES_CFG_ADDR, tmp);

    // crop config
    dvp_module_crop_cfg(&(cfg->crop));

    if (cfg->mode == DVP_MODE_BINA) {
        // set start ddr address
        tmp = DVP_RF0_READ_REG(CFG_START_ADDR0_ADDR);
        REG_FIELD_SET(START_ADDR0, tmp, 0);
        DVP_RF0_WRITE_REG(CFG_START_ADDR0_ADDR, tmp);
        tmp = DVP_RF0_READ_REG(CFG_START_ADDR3_ADDR);
        REG_FIELD_SET(START_ADDR3, tmp, 0);
        DVP_RF0_WRITE_REG(CFG_START_ADDR3_ADDR, tmp);

        // row col cnt for dvp
        tmp = DVP_RF0_READ_REG(CFG_RAW_ROW_CNT_ADDR);
        REG_FIELD_SET(RAW_ROW_CNT_SHD, tmp, 720);
        DVP_RF0_WRITE_REG(CFG_RAW_ROW_CNT_ADDR, tmp);
        tmp = DVP_RF0_READ_REG(CFG_RAW_COL_CNT_ADDR);
        REG_FIELD_SET(RAW_COL_CNT_SHD, tmp, 1024);
        DVP_RF0_WRITE_REG(CFG_RAW_COL_CNT_ADDR, tmp);

        // bina config
        tmp = DVP_RF0_READ_REG(CFG_BINA_CTRL_ADDR);
        REG_FIELD_SET(BINA_EN_SHD, tmp, 0x1);   // bina en shd
        REG_FIELD_SET(BINA_STORE_EN, tmp, 0x0); // 0: ram 1: ram & psram
        REG_FIELD_SET(BINA_BLOCK_SEL_SHD, tmp, 1);  // 0: 7X7 1: 9X9
        DVP_RF0_WRITE_REG(CFG_BINA_CTRL_ADDR, tmp);

        // bina factor
        tmp = DVP_RF0_READ_REG(CFG_BINA_FACTOR_ADDR);
        REG_FIELD_SET(BINA_THOSD_SHD, tmp, 0x5);
        REG_FIELD_SET(BINA_C1_SHD, tmp, 0x21);
        REG_FIELD_SET(BINA_C2_SHD, tmp, 0x7);
        DVP_RF0_WRITE_REG(CFG_BINA_FACTOR_ADDR, tmp);

        // bina frame addr
        tmp = DVP_RF0_READ_REG(CFG_BINA_FRAME_ADDR_ADDR);
        REG_FIELD_SET(FRAME_END_ADDR_RF, tmp, 0x72FF);
        REG_FIELD_SET(FRAME_ADDR_SW, tmp, 0);
        DVP_RF0_WRITE_REG(CFG_BINA_FRAME_ADDR_ADDR, tmp);

        // bina aec
        tmp = DVP_RF0_READ_REG(CFG_BINA_AEC_ADDR);
        REG_FIELD_SET(BINA_AEC_EN_RF, tmp, 1);
        DVP_RF0_WRITE_REG(CFG_BINA_AEC_ADDR, tmp);

        // dcam ctrl
        tmp = DVP_RF0_READ_REG(CFG_DCAM_CTRL_ADDR);
        REG_FIELD_SET(DVP_EN_SHD, tmp, 1);
        REG_FIELD_SET(CROP_EN_SHD, tmp, 1);     // crop enable
        REG_FIELD_SET(RAW_Y_EN_SHD, tmp, 0);    // raw y disable
        REG_FIELD_SET(FRAME_EN_RF_SHD, tmp, 1); // rx frame enable
        REG_FIELD_SET(BURST_LEN_SHD, tmp, 0x1f); // burst len 0-63, unit is byte
        DVP_RF0_WRITE_REG(CFG_DCAM_CTRL_ADDR, tmp);
    } else if (cfg->mode == DVP_MODE_RAW) {

        // ena int
        tmp = DVP_RF0_READ_REG(CFG_DVP_INT_ENA_ADDR);
        REG_FIELD_SET(DCAM_FRM_DONE_ENA, tmp, 1);
        DVP_RF0_WRITE_REG(CFG_DVP_INT_ENA_ADDR, tmp);
        // set start ddr address
        tmp = DVP_RF0_READ_REG(CFG_START_ADDR0_ADDR);
        REG_FIELD_SET(START_ADDR0, tmp, DVP_CACHE_START0_ADDR);// offset : 4M
        DVP_RF0_WRITE_REG(CFG_START_ADDR0_ADDR, tmp);
        tmp = DVP_RF0_READ_REG(CFG_START_ADDR3_ADDR);
        REG_FIELD_SET(START_ADDR3, tmp, DVP_CACHE_START3_ADDR); // offset : 6M
        DVP_RF0_WRITE_REG(CFG_START_ADDR3_ADDR, tmp);

        // row col cnt for dvp
        tmp = DVP_RF0_READ_REG(CFG_RAW_ROW_CNT_ADDR);
        REG_FIELD_SET(RAW_ROW_CNT_SHD, tmp, 720);
        DVP_RF0_WRITE_REG(CFG_RAW_ROW_CNT_ADDR, tmp);
        tmp = DVP_RF0_READ_REG(CFG_RAW_COL_CNT_ADDR);
        REG_FIELD_SET(RAW_COL_CNT_SHD, tmp, 1280);
        DVP_RF0_WRITE_REG(CFG_RAW_COL_CNT_ADDR, tmp);

        // disable bina en
        tmp = DVP_RF0_READ_REG(CFG_BINA_CTRL_ADDR);
        REG_FIELD_SET(BINA_EN_SHD, tmp, 0x0);   // bina en shd
        DVP_RF0_WRITE_REG(CFG_BINA_CTRL_ADDR, tmp);

        // dest vitual width
        tmp = DVP_RF0_READ_REG(CFG_DS_CFG_ADDR);
        REG_FIELD_SET(DST_VIRTUAL_WIDTH, tmp, 1024); // virtual width
        DVP_RF0_WRITE_REG(CFG_DS_CFG_ADDR, tmp);

        // dcam ctrl
        tmp = DVP_RF0_READ_REG(CFG_DCAM_CTRL_ADDR);
        REG_FIELD_SET(DVP_EN_SHD, tmp, 1);
        REG_FIELD_SET(CROP_EN_SHD, tmp, 1);     // crop enable
        REG_FIELD_SET(RAW_Y_EN_SHD, tmp, 1);    // raw y en
        REG_FIELD_SET(FRAME_EN_RF_SHD, tmp, 1); // rx frame enable
        REG_FIELD_SET(BURST_LEN_SHD, tmp, 0x1f); // burst len 0-63, unit is byte
        DVP_RF0_WRITE_REG(CFG_DCAM_CTRL_ADDR, tmp);
    } else {
        return;
    }

    return;
}

void ai_ref_pic_capture()
{
    // capture a picture for reference
    uint32_t tmp;
    tmp = AI_GLB_READ_REG(CFG_AI_GLB_CFG0_ADDR);
    REG_FIELD_SET(REF_PIC_CAPTURE, tmp, 1);
    AI_GLB_WRITE_REG(CFG_AI_GLB_CFG0_ADDR, tmp);
}
#if 0
void ai_depth_ref_test()
{
    uint32_t tmp;
    uint32_t x_pixel, y_pixel;
    uint32_t ai_trans_len;
    // prepare org data, and put it in the first ai ram
    #if 0
    uint8_t *input = (uint8_t *) AI_INNER_RAM0_ADDR;
    os_mem_cpy(input,  input_bin, input_bin_len);
    uint8_t *ref = (uint8_t *) AI_INNER_RAM1_ADDR;
    os_mem_cpy(ref,  ref_bin, ref_bin_len);
    #else
    volatile uint8_t *reg = (volatile uint8_t *) AI_INNER_RAM0_ADDR;
    volatile uint8_t *reg1 = (volatile uint8_t *) AI_INNER_RAM1_ADDR;
    for(uint32_t i = 0; i < 1024; i++) {
        *(reg + i) = i;
    }
    for(uint32_t i = 0; i < 1024; i++) {
        *(reg1 + i) = i + 1;
    }
    #endif


    // prepare ref data, and put it in the second ai ram

    // k3d config
    // k3d enable

    // k3d enable && reset
    tmp = AHB_RF_READ_REG(CFG_AHB_REG1_ADDR);
    tmp |= 0x80;
    tmp |= 0x800;
    AHB_RF_WRITE_REG(CFG_AHB_REG1_ADDR, tmp);

    tmp = AHB_RF_READ_REG(CFG_AHB_REG0_ADDR);
    tmp |= 0x80;
    tmp |= 0x800;
    AHB_RF_WRITE_REG(CFG_AHB_REG0_ADDR, tmp);

    tmp = AHB_RF_READ_REG(CFG_AHB_REG0_ADDR);
    tmp &= ~0x80;
    tmp &= ~0x800;
    AHB_RF_WRITE_REG(CFG_AHB_REG0_ADDR, tmp);

    tmp = AI_GLB_READ_REG(CFG_AI_GLB_CFG0_ADDR);
    REG_FIELD_SET(K3D_ENA, tmp, 1);
    REG_FIELD_SET(REF_PIC_CAPTURE, tmp, 1); // set this to 1, for cratch ref
    AI_GLB_WRITE_REG(CFG_AI_GLB_CFG0_ADDR, tmp);

    // set img 640*720
    x_pixel = 1024;
    y_pixel = 720;
    tmp = K3D_READ_REG(CFG_K3D_FRM_CFG_ADDR);
    REG_FIELD_SET(FRM_Y_MAX, tmp, y_pixel);
    REG_FIELD_SET(FRM_X_MAX, tmp, x_pixel);
    K3D_WRITE_REG(CFG_K3D_FRM_CFG_ADDR, tmp);

    // k3d frame config
    tmp = K3D_READ_REG(CFG_K3D_RFRM_INI_ADDR);
    REG_FIELD_SET(RFRM_Y_INI, tmp, 0xFF3);
    REG_FIELD_SET(RFRM_X_INI, tmp, 0xFFE);
    K3D_WRITE_REG(CFG_K3D_RFRM_INI_ADDR, tmp);

    tmp = K3D_READ_REG(CFG_K3D_RBLK_CFG_ADDR);
    REG_FIELD_SET(RFRM_X_EXD, tmp, 2);
    REG_FIELD_SET(RBLK_US_MAX, tmp, 3);
    REG_FIELD_SET(RBLK_LS_MAX, tmp, 105);
    REG_FIELD_SET(RBLK_Y_MAX, tmp, 42);
    K3D_WRITE_REG(CFG_K3D_RBLK_CFG_ADDR, tmp);

    tmp = K3D_READ_REG(CFG_K3D_CBLK_CFG_ADDR);
    REG_FIELD_SET(CFRM_Y_INI, tmp, 0xFF4);
    REG_FIELD_SET(CBLK_Y_MAX, tmp, 40);
    K3D_WRITE_REG(CFG_K3D_CBLK_CFG_ADDR, tmp);

    tmp = K3D_READ_REG(CFG_K3D_MISC_CFG_ADDR);
    REG_FIELD_SET(BLK_CHK_ENA, tmp, 1);
#if K3D_SUB_P
    REG_FIELD_SET(BLK_SUBP_ENA, tmp, 1);
#else
    REG_FIELD_SET(BLK_SUBP_ENA, tmp, 0);
#endif
    REG_FIELD_SET(BLK_START_Y, tmp, 0xF);
    REG_FIELD_SET(BLK_START_X, tmp, 0xCC);
    K3D_WRITE_REG(CFG_K3D_MISC_CFG_ADDR, tmp);

    tmp = K3D_READ_REG(CFG_K3D_OUT_CFG_ADDR);
    REG_FIELD_SET(BLK_VLD_TH, tmp, 0xFF);
    REG_FIELD_SET(BLK_SUM_CFG, tmp, 0xFF);
    REG_FIELD_SET(BLK_VEC_CFG, tmp, 0x0740);
    K3D_WRITE_REG(CFG_K3D_OUT_CFG_ADDR, tmp);

    tmp = K3D_READ_REG(CFG_K3D_DONE_ST_ADDR);
    //REG_FIELD_SET(K3D_INT_ENA, tmp, 0);
    REG_FIELD_SET(K3D_DONE, tmp, 0);
    K3D_WRITE_REG(CFG_K3D_DONE_ST_ADDR, tmp);

    // ai global register config
    ai_trans_len = x_pixel * y_pixel * 2 / 4; // dword
    tmp = AI_GLB_READ_REG(CFG_AI_MST_CFG1_ADDR);
    REG_FIELD_SET(AI_MST_TRANS_LEN, tmp, ai_trans_len);
    AI_GLB_WRITE_REG(CFG_AI_MST_CFG1_ADDR, tmp);

    uint32_t ai_k3d_16l_len;
    ai_k3d_16l_len = x_pixel * 16 * 2 / 4; // dword
    tmp = AI_GLB_READ_REG(CFG_AI_MST_CFG2_ADDR);
    REG_FIELD_SET(AI_K3D_16L_LEN, tmp, ai_k3d_16l_len);
    AI_GLB_WRITE_REG(CFG_AI_MST_CFG2_ADDR, tmp);

    // ram offset, unit is word
    tmp = AI_GLB_READ_REG(CFG_AI_RAM_SADDR_ADDR);
    REG_FIELD_SET(AI_MST_RAM_SADDR, tmp, AI_INNER_RAM_START_ADDR);
    AI_GLB_WRITE_REG(CFG_AI_RAM_SADDR_ADDR, tmp);

    // ram offset, unit is word
    tmp = AI_GLB_READ_REG(CFG_AI_RAM_EADDR_ADDR);
    REG_FIELD_SET(AI_MST_RAM_EADDR, tmp, AI_INNER_RAM_END_ADDR);
    AI_GLB_WRITE_REG(CFG_AI_RAM_EADDR_ADDR, tmp);

    // ddr offset, unit is word
    tmp = AI_GLB_READ_REG(CFG_AI_DMC_SADDR_ADDR);
    REG_FIELD_SET(AI_MST_DMC_SADDR, tmp, AI_DDR_START_ADDR);
    AI_GLB_WRITE_REG(CFG_AI_DMC_SADDR0_ADDR, tmp);

    tmp = AI_GLB_READ_REG(CFG_AI_MST_ST_ADDR);
    REG_FIELD_SET(K3D_OUT_RAM_EMP, tmp, 0);
    REG_FIELD_SET(K3D_OUT_RAM_FULL, tmp, 0);
    REG_FIELD_SET(K3D_OUT_RAM_RPTR, tmp, 0);
    REG_FIELD_SET(K3D_OUT_RAM_WPTR, tmp, 0);
    REG_FIELD_SET(DCAM_BIN_RAM_FORCE_DONE, tmp, 0);
    REG_FIELD_SET(DCAM_BIN_RAM_EMP, tmp, 0);
    REG_FIELD_SET(DCAM_BIN_RAM_FULL, tmp, 0);
    REG_FIELD_SET(DCAM_BIN_RAM_RPTR, tmp, 0);
    REG_FIELD_SET(DCAM_BIN_RAM_WPTR, tmp, 0);
    REG_FIELD_SET(AI_MST_DONE, tmp, 0);
    AI_GLB_WRITE_REG(CFG_AI_MST_ST_ADDR, tmp);

    tmp = AI_GLB_READ_REG(CFG_AI_MST_CFG0_ADDR);
    REG_FIELD_SET(AI_MST_BURST_LEN, tmp, 64);
    REG_FIELD_SET(AI_MST_K3D_MODE, tmp, 1);
    REG_FIELD_SET(AI_MST_RW, tmp, 0);
    REG_FIELD_SET(AI_MST_ENA, tmp, 1);
    AI_GLB_WRITE_REG(CFG_AI_MST_CFG0_ADDR, tmp);

    tmp = K3D_READ_REG(CFG_K3D_CTRL_ADDR);
    REG_FIELD_SET(K3D_OUT_SW_MAX, tmp, 0x45);
    REG_FIELD_SET(K3D_MODE, tmp, 0x3);
    REG_FIELD_SET(K3D_AUTO_ENA, tmp, 0);
    REG_FIELD_SET(K3D_SUM_OUT_ENA, tmp, 0);
    REG_FIELD_SET(K3D_FORCE_START, tmp, 1);
    K3D_WRITE_REG(CFG_K3D_CTRL_ADDR, tmp);

    // dvp bina mode, and with crop
    dvp_reg_cfg_t dvp_cfg = {0};
    dvp_cfg.mode = DVP_MODE_BINA;
    dvp_cfg.crop.ena = 1;
    dvp_cfg.crop.x0 = 0xff;
    dvp_cfg.crop.y0 = 0x0;
    dvp_cfg.crop.x1 = 0x4ff;
    dvp_cfg.crop.y1 = 0x2d0;
    dvp_module_cfg(&dvp_cfg);

    while(1) {
        tmp = K3D_READ_REG(CFG_K3D_DONE_ST_ADDR);
        if (tmp & 0x1) {
            iot_printf("k3d done\n");
            break;
        }
    }

    // todo dump data from ddr
    while(1) {

    }

}
#endif

void ai_ram_auto_mode_cfg()
{
    uint32_t tmp;

    // dvp enable, ai disable
    tmp = AHB_RF_READ_REG(CFG_AHB_REG1_ADDR);
    REG_FIELD_SET(AI_EB, tmp, 0);
    REG_FIELD_SET(DVP0_EB, tmp, 1);
    AHB_RF_WRITE_REG(CFG_AHB_REG1_ADDR, tmp);

    tmp = AHB_RF_READ_REG(CFG_AHB_REG0_ADDR);
    REG_FIELD_SET(AI_SOFT_RST, tmp, 1);
    REG_FIELD_SET(DVP0_SOFT_RST, tmp, 1);
    AHB_RF_WRITE_REG(CFG_AHB_REG0_ADDR, tmp);

    tmp = AHB_RF_READ_REG(CFG_AHB_REG0_ADDR);
    REG_FIELD_SET(DVP0_SOFT_RST, tmp, 0);
    AHB_RF_WRITE_REG(CFG_AHB_REG0_ADDR, tmp);

    dvp_reg_cfg_t dvp_cfg = {0};
    dvp_cfg.mode = DVP_MODE_RAW;
    dvp_cfg.crop.ena = 1;
    dvp_cfg.crop.x0 = 0x1;
    dvp_cfg.crop.y0 = 0x0;
    dvp_cfg.crop.x1 = 0x400;
    dvp_cfg.crop.y1 = 0x2cf;
    dvp_module_cfg(&dvp_cfg);
}

// auto mode: ddr output address : 0x0, size: 1024 * 720 * 2
void ai_depth_auto_mode_cfg()
{
    uint32_t tmp;
    uint32_t x_pixel, y_pixel;
    uint32_t ai_trans_len;

    // k3d config
    // ai dvp enable && reset
    tmp = AHB_RF_READ_REG(CFG_AHB_REG1_ADDR);
    REG_FIELD_SET(AI_EB, tmp, 1);
    REG_FIELD_SET(DVP0_EB, tmp, 1);
    AHB_RF_WRITE_REG(CFG_AHB_REG1_ADDR, tmp);

    tmp = AHB_RF_READ_REG(CFG_AHB_REG0_ADDR);
    REG_FIELD_SET(AI_SOFT_RST, tmp, 1);
    REG_FIELD_SET(DVP0_SOFT_RST, tmp, 1);
    AHB_RF_WRITE_REG(CFG_AHB_REG0_ADDR, tmp);

    tmp = AHB_RF_READ_REG(CFG_AHB_REG0_ADDR);
    REG_FIELD_SET(AI_SOFT_RST, tmp, 0);
    REG_FIELD_SET(DVP0_SOFT_RST, tmp, 0);
    AHB_RF_WRITE_REG(CFG_AHB_REG0_ADDR, tmp);

    tmp = AI_GLB_READ_REG(CFG_AI_GLB_CFG0_ADDR);
    REG_FIELD_SET(K3D_ENA, tmp, 1);
    AI_GLB_WRITE_REG(CFG_AI_GLB_CFG0_ADDR, tmp);

    // set img 640*720
    x_pixel = 1024;
    y_pixel = 720;
    tmp = K3D_READ_REG(CFG_K3D_FRM_CFG_ADDR);
    REG_FIELD_SET(FRM_Y_MAX, tmp, y_pixel);
    REG_FIELD_SET(FRM_X_MAX, tmp, x_pixel);
    K3D_WRITE_REG(CFG_K3D_FRM_CFG_ADDR, tmp);

    // k3d frame config
    tmp = K3D_READ_REG(CFG_K3D_RFRM_INI_ADDR);
    REG_FIELD_SET(RFRM_Y_INI, tmp, 0xFF3);
    REG_FIELD_SET(RFRM_X_INI, tmp, 0xFFE);
    K3D_WRITE_REG(CFG_K3D_RFRM_INI_ADDR, tmp);

    tmp = K3D_READ_REG(CFG_K3D_RBLK_CFG_ADDR);
    REG_FIELD_SET(RFRM_X_EXD, tmp, 2);
    REG_FIELD_SET(RBLK_US_MAX, tmp, 3);
    REG_FIELD_SET(RBLK_LS_MAX, tmp, 105);
    REG_FIELD_SET(RBLK_Y_MAX, tmp, 42);
    K3D_WRITE_REG(CFG_K3D_RBLK_CFG_ADDR, tmp);

    tmp = K3D_READ_REG(CFG_K3D_CBLK_CFG_ADDR);
    REG_FIELD_SET(CFRM_Y_INI, tmp, 0xFF4);
    REG_FIELD_SET(CBLK_Y_MAX, tmp, 40);
    K3D_WRITE_REG(CFG_K3D_CBLK_CFG_ADDR, tmp);

    tmp = K3D_READ_REG(CFG_K3D_MISC_CFG_ADDR);
    REG_FIELD_SET(BLK_CHK_ENA, tmp, 1);
#if K3D_SUB_P
    REG_FIELD_SET(BLK_SUBP_ENA, tmp, 1);
#else
    REG_FIELD_SET(BLK_SUBP_ENA, tmp, 0);
#endif
    REG_FIELD_SET(BLK_START_Y, tmp, 0xF);
    REG_FIELD_SET(BLK_START_X, tmp, 0xCC);
    K3D_WRITE_REG(CFG_K3D_MISC_CFG_ADDR, tmp);

    tmp = K3D_READ_REG(CFG_K3D_OUT_CFG_ADDR);
    REG_FIELD_SET(BLK_VLD_TH, tmp, 0xFF);
    REG_FIELD_SET(BLK_SUM_CFG, tmp, 0xFF);
    REG_FIELD_SET(BLK_VEC_CFG, tmp, 0x0740);
    K3D_WRITE_REG(CFG_K3D_OUT_CFG_ADDR, tmp);

    tmp = K3D_READ_REG(CFG_K3D_DONE_ST_ADDR);
    REG_FIELD_SET(K3D_DONE, tmp, 0);
    K3D_WRITE_REG(CFG_K3D_DONE_ST_ADDR, tmp);

    // ai global register config
    ai_trans_len = x_pixel * y_pixel * 2 / 4; // dword
    tmp = AI_GLB_READ_REG(CFG_AI_MST_CFG1_ADDR);
    REG_FIELD_SET(AI_MST_TRANS_LEN, tmp, ai_trans_len);
    AI_GLB_WRITE_REG(CFG_AI_MST_CFG1_ADDR, tmp);

    uint32_t ai_k3d_16l_len;
    ai_k3d_16l_len = x_pixel * 16 * 2 / 4; // dword
    tmp = AI_GLB_READ_REG(CFG_AI_MST_CFG2_ADDR);
    REG_FIELD_SET(AI_K3D_16L_LEN, tmp, ai_k3d_16l_len);
    AI_GLB_WRITE_REG(CFG_AI_MST_CFG2_ADDR, tmp);

    // ram offset, unit is word
    tmp = AI_GLB_READ_REG(CFG_AI_RAM_SADDR_ADDR);
    REG_FIELD_SET(AI_MST_RAM_SADDR, tmp, AI_INNER_RAM_START_ADDR);
    AI_GLB_WRITE_REG(CFG_AI_RAM_SADDR_ADDR, tmp);

    // ram offset, unit is word
    tmp = AI_GLB_READ_REG(CFG_AI_RAM_EADDR_ADDR);
    REG_FIELD_SET(AI_MST_RAM_EADDR, tmp, AI_INNER_RAM_END_ADDR);
    AI_GLB_WRITE_REG(CFG_AI_RAM_EADDR_ADDR, tmp);

    // ddr offset, unit is word
    tmp = AI_GLB_READ_REG(CFG_AI_DMC_SADDR0_ADDR);
    REG_FIELD_SET(AI_MST_DMC_SADDR0, tmp, AI_DDR_START_ADDR);
    AI_GLB_WRITE_REG(CFG_AI_DMC_SADDR0_ADDR, tmp);

    tmp = AI_GLB_READ_REG(CFG_AI_MST_ST_ADDR);
    REG_FIELD_SET(K3D_OUT_RAM_EMP, tmp, 0);
    REG_FIELD_SET(K3D_OUT_RAM_FULL, tmp, 0);
    REG_FIELD_SET(K3D_OUT_RAM_RPTR, tmp, 0);
    REG_FIELD_SET(K3D_OUT_RAM_WPTR, tmp, 0);
    REG_FIELD_SET(DCAM_FRM_FORCE_DONE, tmp, 0);
    REG_FIELD_SET(DCAM_BIN_RAM_EMP, tmp, 0);
    REG_FIELD_SET(DCAM_BIN_RAM_FULL, tmp, 0);
    REG_FIELD_SET(DCAM_BIN_RAM_RPTR, tmp, 0);
    REG_FIELD_SET(DCAM_BIN_RAM_WPTR, tmp, 0);
    REG_FIELD_SET(AI_MST_DONE, tmp, 0);
    AI_GLB_WRITE_REG(CFG_AI_MST_ST_ADDR, tmp);

    tmp = AI_GLB_READ_REG(CFG_AI_MST_CFG0_ADDR);
    REG_FIELD_SET(AI_MST_BURST_LEN, tmp, 64);
    REG_FIELD_SET(AI_MST_K3D_MODE, tmp, 1);
    REG_FIELD_SET(AI_MST_RW, tmp, 0);
    REG_FIELD_SET(AI_MST_ENA, tmp, 1);
    AI_GLB_WRITE_REG(CFG_AI_MST_CFG0_ADDR, tmp);

    tmp = K3D_READ_REG(CFG_K3D_CTRL_ADDR);
    REG_FIELD_SET(K3D_OUT_SW_MAX, tmp, 0x45);
    REG_FIELD_SET(K3D_MODE, tmp, 0x3);
    REG_FIELD_SET(K3D_AUTO_ENA, tmp, 1);
    //REG_FIELD_SET(K3D_AUTO_ENA, tmp, 0);
    REG_FIELD_SET(K3D_SUM_OUT_ENA, tmp, 0);
    REG_FIELD_SET(K3D_FORCE_START, tmp, 0);
    //REG_FIELD_SET(K3D_FORCE_START, tmp, 1);
    K3D_WRITE_REG(CFG_K3D_CTRL_ADDR, tmp);

    dvp_reg_cfg_t dvp_cfg = {0};
    dvp_cfg.mode = DVP_MODE_BINA;
    dvp_cfg.crop.ena = 1;
    dvp_cfg.crop.x0 = 0xff;
    dvp_cfg.crop.y0 = 0x0;
    dvp_cfg.crop.x1 = 0x4ff;
    dvp_cfg.crop.y1 = 0x2d0;
    dvp_module_cfg(&dvp_cfg);

#if 0
    // test case: when ai master done,
    uint32_t g_cnt = 0;
    while(1) {
        while(1) {
            tmp = AI_GLB_READ_REG(CFG_AI_MST_ST_ADDR);
            if (tmp & 0x1) {
                iot_printf("ai master done: %d\n", g_cnt);
                g_cnt++;

                // debug: auto ena disable
                tmp = K3D_READ_REG(CFG_K3D_CTRL_ADDR);
                REG_FIELD_SET(K3D_AUTO_ENA, tmp, 0);
                K3D_WRITE_REG(CFG_K3D_CTRL_ADDR, tmp);

                // todo: data transfer

                // debug: auto ena enable
                tmp = K3D_READ_REG(CFG_K3D_CTRL_ADDR);
                REG_FIELD_SET(K3D_AUTO_ENA, tmp, 1);
                K3D_WRITE_REG(CFG_K3D_CTRL_ADDR, tmp);
                break;
            }
        }

        // clear master done
        tmp = AI_GLB_READ_REG(CFG_AI_MST_ST_ADDR);
        tmp &= ~0x1;
        AI_GLB_WRITE_REG(CFG_AI_MST_ST_ADDR, tmp);
        // clear k3d done
        tmp = K3D_READ_REG(CFG_K3D_DONE_ST_ADDR);
        tmp &= ~0x1;
        K3D_WRITE_REG(CFG_K3D_DONE_ST_ADDR, tmp);
        // enable ai master or k3d force enable
        tmp = AI_GLB_READ_REG(CFG_AI_MST_CFG0_ADDR);
        tmp |= 0x1;
        AI_GLB_WRITE_REG(CFG_AI_MST_CFG0_ADDR, tmp);
    }
#endif
}

void ai_poll_done()
{
    uint32_t tmp;
  uint32_t g_cnt = 0;
     while(1) {
        while(1) {
            tmp = AI_GLB_READ_REG(CFG_AI_MST_ST_ADDR);
            if (tmp & 0x1) {
                iot_printf("ai master done: %d\n", g_cnt);
                g_cnt++;
                // debug: auto ena disable
                tmp = K3D_READ_REG(CFG_K3D_CTRL_ADDR);
                REG_FIELD_SET(K3D_AUTO_ENA, tmp, 0);
                K3D_WRITE_REG(CFG_K3D_CTRL_ADDR, tmp);

                // clear master done
                tmp = AI_GLB_READ_REG(CFG_AI_MST_ST_ADDR);
                tmp &= ~0x1;
                AI_GLB_WRITE_REG(CFG_AI_MST_ST_ADDR, tmp);
                // clear k3d done
                tmp = K3D_READ_REG(CFG_K3D_DONE_ST_ADDR);
                tmp &= ~0x1;
                AI_GLB_WRITE_REG(CFG_K3D_DONE_ST_ADDR, tmp);

                // todo: data transfer

                // debug: auto ena enable
                tmp = K3D_READ_REG(CFG_K3D_CTRL_ADDR);
                REG_FIELD_SET(K3D_AUTO_ENA, tmp, 1);
                K3D_WRITE_REG(CFG_K3D_CTRL_ADDR, tmp);

                //
                break;
            }
        }

        // ai master enable
        tmp = AI_GLB_READ_REG(CFG_AI_MST_CFG0_ADDR);
        REG_FIELD_SET(AI_MST_ENA, tmp, 1);
        AI_GLB_WRITE_REG(CFG_AI_MST_CFG0_ADDR, tmp);
    }
}

uint32_t dvp_get_frame_address()
{
    return 0x18000000;
}


uint32_t dvp_check_frame_done()
{
#if 1
    uint32_t tmp;

    tmp = DVP_RF0_READ_REG(CFG_DVP_INT_RAW_ADDR);

    return REG_FIELD_GET(TX_FRAME_OVER_RAW, tmp);
#endif
}

void dvp_clear_frame_done()
{
    uint32_t tmp;
    tmp = DVP_RF0_READ_REG(CFG_DVP_INT_CLR_ADDR);
    REG_FIELD_SET(TX_FRAME_OVER_CLR, tmp, 1);
    DVP_RF0_WRITE_REG(CFG_DVP_INT_CLR_ADDR, tmp);
}

void dvp_disable_ram_auto()
{
    uint32_t tmp;
    //tmp = DVP_RF0_READ_REG(CFG_DCAM_CTRL_ADDR);
    tmp = 0;
    DVP_RF0_WRITE_REG(CFG_DCAM_CTRL_ADDR, tmp);
}

void dvp_enable_ram_auto()
{
    uint32_t tmp;
    // dcam ctrl
    tmp = DVP_RF0_READ_REG(CFG_DCAM_CTRL_ADDR);
    REG_FIELD_SET(DVP_EN_SHD, tmp, 1);
    REG_FIELD_SET(CROP_EN_SHD, tmp, 1);     // crop enable
    REG_FIELD_SET(RAW_Y_EN_SHD, tmp, 1);    // raw y disable
    REG_FIELD_SET(FRAME_EN_RF_SHD, tmp, 1); // rx frame enable
    REG_FIELD_SET(BURST_LEN_SHD, tmp, 0x1f); // burst len 0-63, unit is byte
    DVP_RF0_WRITE_REG(CFG_DCAM_CTRL_ADDR, tmp);
}

uint32_t dvp_get_idle_frame_addr()
{
    uint32_t tmp;
    tmp = DVP_RF0_READ_REG(CFG_DES_CFG_ADDR);

    if(REG_FIELD_GET(EMC_ADDR_FLAG, tmp) == 1) {
        tmp = DVP_RF0_READ_REG(CFG_START_ADDR3_ADDR);
        return (REG_FIELD_GET(START_ADDR3, tmp) + K3D_CACHE_PRIME_ADDR);
    } else {
        tmp = DVP_RF0_READ_REG(CFG_START_ADDR0_ADDR);
        return (REG_FIELD_GET(START_ADDR0, tmp) + K3D_CACHE_PRIME_ADDR);
    }
}

uint32_t ai_get_frame_address()
{
    return K3D_CACHE_PRIME_ADDR;
}

uint32_t ai_check_master_done()
{
    uint32_t tmp;

    tmp = AI_GLB_READ_REG(CFG_AI_MST_ST_ADDR);

    return REG_FIELD_GET(AI_MST_DONE, tmp);
}

void ai_disable_auto()
{
    uint32_t tmp;

    tmp = K3D_READ_REG(CFG_K3D_CTRL_ADDR);
    REG_FIELD_SET(K3D_AUTO_ENA, tmp, 0);
    K3D_WRITE_REG(CFG_K3D_CTRL_ADDR, tmp);
}

void ai_enable_auto()
{
    uint32_t tmp;

    tmp = K3D_READ_REG(CFG_K3D_CTRL_ADDR);
    REG_FIELD_SET(K3D_AUTO_ENA, tmp, 1);
    K3D_WRITE_REG(CFG_K3D_CTRL_ADDR, tmp);
}

void ai_clear_master_done()
{
    uint32_t tmp;
    // clear master done
    tmp = AI_GLB_READ_REG(CFG_AI_MST_ST_ADDR);
    tmp &= ~0x1;
    AI_GLB_WRITE_REG(CFG_AI_MST_ST_ADDR, tmp);
    // clear k3d done
    tmp = K3D_READ_REG(CFG_K3D_DONE_ST_ADDR);
    tmp &= ~0x1;
    K3D_WRITE_REG(CFG_K3D_DONE_ST_ADDR, tmp);
}

void ai_enable_master()
{
    uint32_t tmp;

    tmp = AI_GLB_READ_REG(CFG_AI_MST_CFG0_ADDR);
    REG_FIELD_SET(AI_MST_ENA, tmp, 1);
    AI_GLB_WRITE_REG(CFG_AI_MST_CFG0_ADDR, tmp);
}