//-----------------------------------
#define CFG_BB_FD_CORR_THR0_ADDR 0x0004
#define SW_TURBO_DEC_SEL_OFFSET 8
#define SW_TURBO_DEC_SEL_MASK 0x00000100
#define SW_FD_CORR_THR0_OFFSET 0
#define SW_FD_CORR_THR0_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_FD_CORR_THR1_ADDR 0x1000

//HW module read/write macro
#define PHY_RX_FD_READ_REG(addr) SOC_READ_REG(PHY_RX_FD_BASEADDR + addr)
#define PHY_RX_FD_WRITE_REG(addr,value) SOC_WRITE_REG(PHY_RX_FD_BASEADDR + addr,value)