//-----------------------------------
#define CFG_GTMR_RVER_ADDR 0x0000
#define GTMR_RF_VER_OFFSET 0
#define GTMR_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_US_CFG_ADDR 0x0004
#define US_GEN_CFG_OFFSET 0
#define US_GEN_CFG_MASK 0x000000FF

//-----------------------------------
#define CFG_US_TMR_CFG_ADDR 0x0008
#define US_TMR_MODE_OFFSET 12
#define US_TMR_MODE_MASK 0x00001000
#define US_TMR_CFG_OFFSET 0
#define US_TMR_CFG_MASK 0x000003FF

//-----------------------------------
#define CFG_MS_TMR_CFG_ADDR 0x000c
#define MS_TMR_MODE_OFFSET 12
#define MS_TMR_MODE_MASK 0x00001000
#define MS_TMR_CFG_OFFSET 0
#define MS_TMR_CFG_MASK 0x000003FF

//-----------------------------------
#define CFG_SEC_TMR_CFG_ADDR 0x0010
#define SEC_TMR_MODE_OFFSET 12
#define SEC_TMR_MODE_MASK 0x00001000
#define SEC_TMR_CFG_OFFSET 0
#define SEC_TMR_CFG_MASK 0x000003FF

//-----------------------------------
#define CFG_TMR_INT_ENA_ADDR 0x00018
#define TMR_INT_ENA_OFFSET 0
#define TMR_INT_ENA_MASK 0x0000003F

//-----------------------------------
#define CFG_TMR_INT_STS_ADDR 0x0001c
#define TMR_INT_STS_OFFSET 0
#define TMR_INT_STS_MASK 0x0000003F

//-----------------------------------
#define CFG_TMR_CNT_ENA_ADDR 0x00024
#define TMR_CNT_ENA_OFFSET 0
#define TMR_CNT_ENA_MASK 0x0000003F

//-----------------------------------
#define CFG_TMR_CNT_CLR_ADDR 0x00028
#define TMR_CNT_CLR_OFFSET 0
#define TMR_CNT_CLR_MASK 0x0000003F

//-----------------------------------
#define CFG_TMR_CNT_STS_ADDR 0x0002c
#define TMR_CNT_STS_OFFSET 0
#define TMR_CNT_STS_MASK 0x0000003F

//HW module read/write macro
#define GTMR_READ_REG(addr) SOC_READ_REG(GTMR_BASEADDR + addr)
#define GTMR_WRITE_REG(addr,value) SOC_WRITE_REG(GTMR_BASEADDR + addr,value)

#define GTMR1_READ_REG(addr) SOC_READ_REG(GTMR1_BASEADDR + addr)
#define GTMR1_WRITE_REG(addr,value) SOC_WRITE_REG(GTMR1_BASEADDR + addr,value)