//----------------------------------- #define CFG_BB_CLOCK_CTRL_ADDR 0x0000 #define SW_MEM_FORCE_ON_OFFSET 7 #define SW_MEM_FORCE_ON_MASK 0x00000080 #define SW_CLK_EN_TD_RX_OFFSET 6 #define SW_CLK_EN_TD_RX_MASK 0x00000040 #define SW_CLK_EN_TD_TX_OFFSET 5 #define SW_CLK_EN_TD_TX_MASK 0x00000020 #define SW_CLK_EN_FFT_OFFSET 4 #define SW_CLK_EN_FFT_MASK 0x00000010 #define SW_CLK_EN_RX_FEC_OFFSET 3 #define SW_CLK_EN_RX_FEC_MASK 0x00000008 #define SW_CLK_EN_TX_FEC_OFFSET 2 #define SW_CLK_EN_TX_FEC_MASK 0x00000004 #define SW_CLK_EN_TURBO_DEC_OFFSET 1 #define SW_CLK_EN_TURBO_DEC_MASK 0x00000002 #define SW_CLK_EN_TURBO_ENC_OFFSET 0 #define SW_CLK_EN_TURBO_ENC_MASK 0x00000001 //----------------------------------- #define CFG_BB_RESET_CTRL_ADDR 0x0004 #define SW_ARST_TD_RX_OFFSET 6 #define SW_ARST_TD_RX_MASK 0x00000040 #define SW_ARST_TD_TX_OFFSET 5 #define SW_ARST_TD_TX_MASK 0x00000020 #define SW_ARST_FFT_OFFSET 4 #define SW_ARST_FFT_MASK 0x00000010 #define SW_ARST_RX_FEC_OFFSET 3 #define SW_ARST_RX_FEC_MASK 0x00000008 #define SW_ARST_TX_FEC_OFFSET 2 #define SW_ARST_TX_FEC_MASK 0x00000004 #define SW_ARST_TURBO_DEC_OFFSET 1 #define SW_ARST_TURBO_DEC_MASK 0x00000002 #define SW_ARST_TURBO_ENC_OFFSET 0 #define SW_ARST_TURBO_ENC_MASK 0x00000001 //----------------------------------- #define CFG_BB_RTL_VERSION_ADDR 0x0008 #define BB_RTL_VERSION_OFFSET 0 #define BB_RTL_VERSION_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_VERSION_ADDR 0x0010 #define SW_BB_VERSION_OFFSET 0 #define SW_BB_VERSION_MASK 0x00000007 //----------------------------------- #define CFG_BB_PRE_CFG_ADDR 0x0014 #define SW_TX_PRS_PRE_NUM_OFFSET 24 #define SW_TX_PRS_PRE_NUM_MASK 0xFF000000 #define SW_TX_PRE_NUM_OFFSET 16 #define SW_TX_PRE_NUM_MASK 0x00FF0000 #define SW_TX_PRE_AMP_OFFSET 5 #define SW_TX_PRE_AMP_MASK 0x000001E0 #define SW_PRE_REF_PHASE_OFFSET 2 #define SW_PRE_REF_PHASE_MASK 0x0000001C #define SW_TX_PRE_MODE_OFFSET 0 #define SW_TX_PRE_MODE_MASK 0x00000003 //----------------------------------- #define CFG_BB_PLD_CFG_ADDR 0x0018 #define SW_RX_TURBO_SOFT_BIT_WIDTH_OFFSET 18 #define SW_RX_TURBO_SOFT_BIT_WIDTH_MASK 0x000C0000 #define SW_RX_TURBO_DEC_LOOP_OFFSET 16 #define SW_RX_TURBO_DEC_LOOP_MASK 0x00030000 #define SW_CI_HBS_DIR_OFFSET 8 #define SW_CI_HBS_DIR_MASK 0x00000100 #define SW_PLD_REF_PHASE_OFFSET 3 #define SW_PLD_REF_PHASE_MASK 0x00000038 #define SW_TX_PLD_MODE_OFFSET 1 #define SW_TX_PLD_MODE_MASK 0x00000006 #define SW_PLD_COPY_MODE_OFFSET 0 #define SW_PLD_COPY_MODE_MASK 0x00000001 //----------------------------------- #define CFG_BB_SW_ACCESS_BUF_ADDR 0x0020 #define SW_ACCESS_CSI_BUF_EN_OFFSET 2 #define SW_ACCESS_CSI_BUF_EN_MASK 0x00000004 #define SW_ACCESS_AGC_GAIN_BUF_EN_OFFSET 1 #define SW_ACCESS_AGC_GAIN_BUF_EN_MASK 0x00000002 #define SW_ACCESS_TMI_BUF_EN_OFFSET 0 #define SW_ACCESS_TMI_BUF_EN_MASK 0x00000001 //----------------------------------- #define CFG_BB_RX_PAUSE_CLR_ADDR 0x0024 #define SW_SOUND_PAUSE_EN_OFFSET 31 #define SW_SOUND_PAUSE_EN_MASK 0x80000000 #define SW_RX_PAUSE_CLR_OFFSET 0 #define SW_RX_PAUSE_CLR_MASK 0x00000001 //----------------------------------- #define CFG_BB_TX_FCC_CTRL_ADDR 0x0050 #define SW_ALWAYS_TX_OFFSET 1 #define SW_ALWAYS_TX_MASK 0x00000002 #define SW_TX_RI_DISABLE_OFFSET 0 #define SW_TX_RI_DISABLE_MASK 0x00000001 //----------------------------------- #define CFG_BB_DPSK_CTRL_ADDR 0x0054 #define SW_IS_DPSK_OFFSET 0 #define SW_IS_DPSK_MASK 0x00000001 //----------------------------------- #define CFG_BB_RAW_DATA_MODE_CTRL_ADDR 0x005c #define SW_IS_RAW_DATA_MODE_OFFSET 0 #define SW_IS_RAW_DATA_MODE_MASK 0x00000001 //----------------------------------- #define CFG_BB_RX_FC_RAW_0_ADDR 0x0060 #define SW_RX_FC_RAW_RD_WORD0_OFFSET 0 #define SW_RX_FC_RAW_RD_WORD0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_RX_FC_RAW_1_ADDR 0x0064 #define SW_RX_FC_RAW_RD_WORD1_OFFSET 0 #define SW_RX_FC_RAW_RD_WORD1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_RX_FC_RAW_2_ADDR 0x0068 #define SW_RX_FC_RAW_RD_WORD2_OFFSET 0 #define SW_RX_FC_RAW_RD_WORD2_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_RX_FC_RAW_3_ADDR 0x006C #define SW_RX_FC_RAW_RD_WORD3_OFFSET 0 #define SW_RX_FC_RAW_RD_WORD3_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_RX_FC_CFG_0_ADDR 0x0070 #define SW_RX_FC_NOW_CFG_WORD0_OFFSET 0 #define SW_RX_FC_NOW_CFG_WORD0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_RX_FC_CFG_1_ADDR 0x0074 #define SW_RX_FC_NOW_CFG_WORD1_OFFSET 0 #define SW_RX_FC_NOW_CFG_WORD1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_RX_FC_CFG_2_ADDR 0x0078 #define SW_RX_FC_NOW_CFG_WORD2_OFFSET 0 #define SW_RX_FC_NOW_CFG_WORD2_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_RX_FC_CFG_3_ADDR 0x007c #define SW_RX_FC_NOW_CFG_VLD_OFFSET 16 #define SW_RX_FC_NOW_CFG_VLD_MASK 0x00010000 #define SW_RX_FC_NOW_CFG_WORD3_OFFSET 0 #define SW_RX_FC_NOW_CFG_WORD3_MASK 0x000000FF //----------------------------------- #define CFG_BB_INT_EN_0_ADDR 0x0080 #define BB_INT_EN_0_OFFSET 0 #define BB_INT_EN_0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_INT_CLR_0_ADDR 0x0084 #define BB_INT_CLR_0_OFFSET 0 #define BB_INT_CLR_0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_INT_MASK_0_ADDR 0x0088 #define BB_INT_MASK_0_OFFSET 0 #define BB_INT_MASK_0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_INT_RAW_0_ADDR 0x008c #define BB_INT_RAW_0_OFFSET 0 #define BB_INT_RAW_0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_INT_EN_1_ADDR 0x0090 #define BB_INT_EN_1_OFFSET 0 #define BB_INT_EN_1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_INT_CLR_1_ADDR 0x0094 #define BB_INT_CLR_1_OFFSET 0 #define BB_INT_CLR_1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_INT_MASK_1_ADDR 0x0098 #define BB_INT_MASK_1_OFFSET 0 #define BB_INT_MASK_1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_INT_RAW_1_ADDR 0x009c #define BB_INT_RAW_1_OFFSET 0 #define BB_INT_RAW_1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_INT_EN_2_ADDR 0x00a0 #define BB_INT_EN_2_OFFSET 0 #define BB_INT_EN_2_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_INT_CLR_2_ADDR 0x00a4 #define BB_INT_CLR_2_OFFSET 0 #define BB_INT_CLR_2_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_INT_MASK_2_ADDR 0x00a8 #define BB_INT_MASK_2_OFFSET 0 #define BB_INT_MASK_2_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_INT_RAW_2_ADDR 0x00ac #define BB_INT_RAW_2_OFFSET 0 #define BB_INT_RAW_2_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_INT_EN_3_ADDR 0x00b0 #define BB_INT_EN_3_OFFSET 0 #define BB_INT_EN_3_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_INT_CLR_3_ADDR 0x00b4 #define BB_INT_CLR_3_OFFSET 0 #define BB_INT_CLR_3_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_INT_MASK_3_ADDR 0x00b8 #define BB_INT_MASK_3_OFFSET 0 #define BB_INT_MASK_3_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_INT_RAW_3_ADDR 0x00bc #define BB_INT_RAW_3_OFFSET 0 #define BB_INT_RAW_3_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_PB_ROBO_ADDR 0x00c0 #define SW_MN_INVERT_OFFSET 1 #define SW_MN_INVERT_MASK 0x00000002 #define SW_IS_NSG_PB_ROBO_OFFSET 0 #define SW_IS_NSG_PB_ROBO_MASK 0x00000001 //----------------------------------- #define CFG_BB_PB_IFS_ADDR 0x00f0 #define SW_RIFS_OFFSET 8 #define SW_RIFS_MASK 0x0000FF00 #define SW_BIFS_OFFSET 0 #define SW_BIFS_MASK 0x000000FF //----------------------------------- #define CFG_BB_FC_OFFSET0_ADDR 0x0100 #define SW_FC_SYMB5_OFFSET_OFFSET 24 #define SW_FC_SYMB5_OFFSET_MASK 0xFF000000 #define SW_FC_SYMB4_OFFSET_OFFSET 16 #define SW_FC_SYMB4_OFFSET_MASK 0x00FF0000 #define SW_FC_SYMB3_OFFSET_OFFSET 8 #define SW_FC_SYMB3_OFFSET_MASK 0x0000FF00 #define SW_FC_SYMB2_OFFSET_OFFSET 0 #define SW_FC_SYMB2_OFFSET_MASK 0x000000FF //----------------------------------- #define CFG_BB_FC_OFFSET1_ADDR 0x0104 #define SW_FC_SYMB9_OFFSET_OFFSET 24 #define SW_FC_SYMB9_OFFSET_MASK 0xFF000000 #define SW_FC_SYMB8_OFFSET_OFFSET 16 #define SW_FC_SYMB8_OFFSET_MASK 0x00FF0000 #define SW_FC_SYMB7_OFFSET_OFFSET 8 #define SW_FC_SYMB7_OFFSET_MASK 0x0000FF00 #define SW_FC_SYMB6_OFFSET_OFFSET 0 #define SW_FC_SYMB6_OFFSET_MASK 0x000000FF //----------------------------------- #define CFG_BB_FC_OFFSET2_ADDR 0x0108 #define SW_FC_SYMB12_OFFSET_OFFSET 16 #define SW_FC_SYMB12_OFFSET_MASK 0x00FF0000 #define SW_FC_SYMB11_OFFSET_OFFSET 8 #define SW_FC_SYMB11_OFFSET_MASK 0x0000FF00 #define SW_FC_SYMB10_OFFSET_OFFSET 0 #define SW_FC_SYMB10_OFFSET_MASK 0x000000FF //----------------------------------- #define CFG_BB_FC_GI_ADDR 0x010C #define SW_FC_GI1_OFFSET 16 #define SW_FC_GI1_MASK 0x07FF0000 #define SW_FC_GI0_RANGE_OFFSET 11 #define SW_FC_GI0_RANGE_MASK 0x00007800 #define SW_FC_GI0_OFFSET 0 #define SW_FC_GI0_MASK 0x000007FF //----------------------------------- #define CFG_BB_PLD_GI0_ADDR 0x0110 #define SW_PLD_GI1_RANGE_OFFSET 27 #define SW_PLD_GI1_RANGE_MASK 0x78000000 #define SW_PLD_GI1_OFFSET 16 #define SW_PLD_GI1_MASK 0x07FF0000 #define SW_PLD_GI0_RANGE_OFFSET 11 #define SW_PLD_GI0_RANGE_MASK 0x00007800 #define SW_PLD_GI0_OFFSET 0 #define SW_PLD_GI0_MASK 0x000007FF //----------------------------------- #define CFG_BB_PLD_GI1_ADDR 0x0114 #define SW_PLD_GI2_OFFSET 0 #define SW_PLD_GI2_MASK 0x000007FF //----------------------------------- #define CFG_BB_CRC_CFG_ADDR 0x0118 #define SW_PLD_CRC_BY_SW_OFFSET 7 #define SW_PLD_CRC_BY_SW_MASK 0x00000080 #define SW_FC_CRC_BY_SW_OFFSET 6 #define SW_FC_CRC_BY_SW_MASK 0x00000040 #define SW_PLD_CRC_INV_OFFSET 5 #define SW_PLD_CRC_INV_MASK 0x00000020 #define SW_FC_CRC_INV_OFFSET 4 #define SW_FC_CRC_INV_MASK 0x00000010 #define SW_PLD_CRC_INITIAL_OFFSET 3 #define SW_PLD_CRC_INITIAL_MASK 0x00000008 #define SW_FC_CRC_INITIAL_OFFSET 2 #define SW_FC_CRC_INITIAL_MASK 0x00000004 #define SW_PLD_CRC_MODE_OFFSET 1 #define SW_PLD_CRC_MODE_MASK 0x00000002 #define SW_FC_CRC_MODE_OFFSET 0 #define SW_FC_CRC_MODE_MASK 0x00000001 //----------------------------------- #define CFG_BB_FC_CRC_REM_ADDR 0x011C #define SW_FC_CRC_REMAIN_OFFSET 0 #define SW_FC_CRC_REMAIN_MASK 0x00FFFFFF //----------------------------------- #define CFG_BB_PLD_CRC_REM_ADDR 0x0120 #define SW_PLD_CRC_REMAIN_OFFSET 0 #define SW_PLD_CRC_REMAIN_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_SOF_FC_FIELD_ADDR 0x0124 #define SW_SOF_SYMB_NUM_START_OFFSET 24 #define SW_SOF_SYMB_NUM_START_MASK 0x7F000000 #define SW_SOF_PB_NUM_START_OFFSET 16 #define SW_SOF_PB_NUM_START_MASK 0x007F0000 #define SW_SOF_DCEM_START_OFFSET 8 #define SW_SOF_DCEM_START_MASK 0x00007F00 #define SW_SOF_DCBM_START_OFFSET 0 #define SW_SOF_DCBM_START_MASK 0x0000007F //----------------------------------- #define CFG_BB_BEA_FC_FIELD_ADDR 0x0128 #define SW_BEA_SYMB_NUM_START_OFFSET 24 #define SW_BEA_SYMB_NUM_START_MASK 0x7F000000 #define SW_BEA_PB_NUM_START_OFFSET 16 #define SW_BEA_PB_NUM_START_MASK 0x007F0000 #define SW_BEA_DCEM_START_OFFSET 8 #define SW_BEA_DCEM_START_MASK 0x00007F00 #define SW_BEA_DCBM_START_OFFSET 0 #define SW_BEA_DCBM_START_MASK 0x0000007F //----------------------------------- #define CFG_BB_R0_B0_TONE_ADDR 0x0200 #define SW_RATE0_BAND0_FC_NUM_OFFSET 27 #define SW_RATE0_BAND0_FC_NUM_MASK 0xF8000000 #define SW_RATE0_BAND0_END_TONE_OFFSET 16 #define SW_RATE0_BAND0_END_TONE_MASK 0x07FF0000 #define SW_RATE0_BAND0_START_TONE_OFFSET 0 #define SW_RATE0_BAND0_START_TONE_MASK 0x000007FF //----------------------------------- #define CFG_BB_R0_B1_TONE_ADDR 0x0204 #define SW_RATE0_BAND1_FC_NUM_OFFSET 27 #define SW_RATE0_BAND1_FC_NUM_MASK 0xF8000000 #define SW_RATE0_BAND1_END_TONE_OFFSET 16 #define SW_RATE0_BAND1_END_TONE_MASK 0x07FF0000 #define SW_RATE0_BAND1_START_TONE_OFFSET 0 #define SW_RATE0_BAND1_START_TONE_MASK 0x000007FF //----------------------------------- #define CFG_BB_R0_B2_TONE_ADDR 0x0208 #define SW_RATE0_BAND2_FC_NUM_OFFSET 27 #define SW_RATE0_BAND2_FC_NUM_MASK 0xF8000000 #define SW_RATE0_BAND2_END_TONE_OFFSET 16 #define SW_RATE0_BAND2_END_TONE_MASK 0x07FF0000 #define SW_RATE0_BAND2_START_TONE_OFFSET 0 #define SW_RATE0_BAND2_START_TONE_MASK 0x000007FF //----------------------------------- #define CFG_BB_R0_B0_VLD_TONE_ADDR 0x020C #define SW_RATE0_BAND0_VLD_TONE_NUM_OFFSET 0 #define SW_RATE0_BAND0_VLD_TONE_NUM_MASK 0x000007FF //----------------------------------- #define CFG_BB_R0_B1_VLD_TONE_ADDR 0x0210 #define SW_RATE0_BAND1_VLD_TONE_NUM_OFFSET 0 #define SW_RATE0_BAND1_VLD_TONE_NUM_MASK 0x000007FF //----------------------------------- #define CFG_BB_R0_B2_VLD_TONE_ADDR 0x0214 #define SW_RATE0_BAND2_VLD_TONE_NUM_OFFSET 0 #define SW_RATE0_BAND2_VLD_TONE_NUM_MASK 0x000007FF //----------------------------------- #define CFG_BB_R1_B0_TONE_ADDR 0x0300 #define SW_RATE1_BAND0_FC_NUM_OFFSET 27 #define SW_RATE1_BAND0_FC_NUM_MASK 0xF8000000 #define SW_RATE1_BAND0_END_TONE_OFFSET 16 #define SW_RATE1_BAND0_END_TONE_MASK 0x07FF0000 #define SW_RATE1_BAND0_START_TONE_OFFSET 0 #define SW_RATE1_BAND0_START_TONE_MASK 0x000007FF //----------------------------------- #define CFG_BB_R1_B1_TONE_ADDR 0x0304 #define SW_RATE1_BAND1_FC_NUM_OFFSET 27 #define SW_RATE1_BAND1_FC_NUM_MASK 0xF8000000 #define SW_RATE1_BAND1_END_TONE_OFFSET 16 #define SW_RATE1_BAND1_END_TONE_MASK 0x07FF0000 #define SW_RATE1_BAND1_START_TONE_OFFSET 0 #define SW_RATE1_BAND1_START_TONE_MASK 0x000007FF //----------------------------------- #define CFG_BB_R1_B2_TONE_ADDR 0x0308 #define SW_RATE1_BAND2_FC_NUM_OFFSET 27 #define SW_RATE1_BAND2_FC_NUM_MASK 0xF8000000 #define SW_RATE1_BAND2_END_TONE_OFFSET 16 #define SW_RATE1_BAND2_END_TONE_MASK 0x07FF0000 #define SW_RATE1_BAND2_START_TONE_OFFSET 0 #define SW_RATE1_BAND2_START_TONE_MASK 0x000007FF //----------------------------------- #define CFG_BB_R1_B0_VLD_TONE_ADDR 0x030C #define SW_RATE1_BAND0_VLD_TONE_NUM_OFFSET 0 #define SW_RATE1_BAND0_VLD_TONE_NUM_MASK 0x000007FF //----------------------------------- #define CFG_BB_R1_B1_VLD_TONE_ADDR 0x0310 #define SW_RATE1_BAND1_VLD_TONE_NUM_OFFSET 0 #define SW_RATE1_BAND1_VLD_TONE_NUM_MASK 0x000007FF //----------------------------------- #define CFG_BB_R1_B2_VLD_TONE_ADDR 0x0314 #define SW_RATE1_BAND2_VLD_TONE_NUM_OFFSET 0 #define SW_RATE1_BAND2_VLD_TONE_NUM_MASK 0x000007FF //----------------------------------- #define CFG_BB_FC_PLD_CNTR_CLR_ADDR 0x0500 #define PLD_CRC_ERROR_CNTR_CLR_OFFSET 3 #define PLD_CRC_ERROR_CNTR_CLR_MASK 0x00000008 #define PLD_CRC_OK_CNTR_CLR_OFFSET 2 #define PLD_CRC_OK_CNTR_CLR_MASK 0x00000004 #define FC_CRC_ERROR_CNTR_CLR_OFFSET 1 #define FC_CRC_ERROR_CNTR_CLR_MASK 0x00000002 #define FC_CRC_OK_CNTR_CLR_OFFSET 0 #define FC_CRC_OK_CNTR_CLR_MASK 0x00000001 //----------------------------------- #define CFG_BB_FC_CRC_OK_CNTR_ADDR 0x0504 #define FC_CRC_OK_CNTR_OFFSET 0 #define FC_CRC_OK_CNTR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_FC_CRC_ERROR_CNTR_ADDR 0x0508 #define FC_CRC_ERROR_CNTR_OFFSET 0 #define FC_CRC_ERROR_CNTR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_PLD_CRC_OK_CNTR_ADDR 0x050C #define PLD_CRC_OK_CNTR_OFFSET 0 #define PLD_CRC_OK_CNTR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_PLD_CRC_ERROR_CNTR_ADDR 0x0510 #define PLD_CRC_ERROR_CNTR_OFFSET 0 #define PLD_CRC_ERROR_CNTR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_DBG_BUS_SEL_ADDR 0x0600 #define BB_DBG_BUS_SEL_OFFSET 0 #define BB_DBG_BUS_SEL_MASK 0x0000000F //----------------------------------- #define CFG_BB_RX_TD_DBG_BUS0_ADDR 0x0604 #define RX_TD_DBG_BUS0_OFFSET 0 #define RX_TD_DBG_BUS0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_RX_TD_DBG_BUS1_ADDR 0x0608 #define RX_TD_DBG_BUS1_OFFSET 0 #define RX_TD_DBG_BUS1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_RX_TD_DBG_BUS2_ADDR 0x060C #define RX_TD_DBG_BUS2_OFFSET 0 #define RX_TD_DBG_BUS2_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_RX_TD_DBG_BUS3_ADDR 0x0610 #define RX_TD_DBG_BUS3_OFFSET 0 #define RX_TD_DBG_BUS3_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_TMI_WORD0_ADDR 0x0614 #define TMI_WORD0_OFFSET 0 #define TMI_WORD0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_TMI_WORD1_ADDR 0x0618 #define TMI_WORD1_OFFSET 0 #define TMI_WORD1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_TMI_WORD2_ADDR 0x061C #define TMI_WORD2_OFFSET 0 #define TMI_WORD2_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_TX_TD_DBG_BUS_ADDR 0x0620 #define TX_TD_DBG_BUS_OFFSET 0 #define TX_TD_DBG_BUS_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_TX_FD_FSM_DBG_BUS_ADDR 0x0624 #define TX_FD_FSM_DBG_BUS_OFFSET 0 #define TX_FD_FSM_DBG_BUS_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_PLD_FEC_DBG_BUS_ADDR 0x0628 #define PLD_FEC_DBG_BUS_OFFSET 0 #define PLD_FEC_DBG_BUS_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_FC_FEC_DBG_BUS_ADDR 0x062C #define FC_FEC_DBG_BUS_OFFSET 0 #define FC_FEC_DBG_BUS_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_PRE_DBG_BUS_ADDR 0x0630 #define PRE_DBG_BUS_OFFSET 0 #define PRE_DBG_BUS_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_AGC_DBG_BUS_ADDR 0x0634 #define AGC_DBG_BUS_OFFSET 0 #define AGC_DBG_BUS_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_CH_EST_DBG_BUS_ADDR 0x0638 #define CH_EST_DBG_BUS_OFFSET 0 #define CH_EST_DBG_BUS_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_CH_EQU_DBG_BUS_ADDR 0x063C #define CH_EQU_DBG_BUS_OFFSET 0 #define CH_EQU_DBG_BUS_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_PLD_DE_FEC_DBG_BUS_ADDR 0x0640 #define PLD_DE_FEC_DBG_BUS_OFFSET 0 #define PLD_DE_FEC_DBG_BUS_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_FC_CRC_DBG_BUS_ADDR 0x0644 #define FC_CRC_DBG_BUS_OFFSET 0 #define FC_CRC_DBG_BUS_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_PB_CRC_DBG_BUS_ADDR 0x0648 #define PB_CRC_DBG_BUS_OFFSET 0 #define PB_CRC_DBG_BUS_MASK 0xFFFFFFFF //----------------------------------- #define CFG_BB_ADA_DUMP_CFG_ADDR 0x0680 #define SW_BB_DUMP_TRIG_SEL_OFFSET 0 #define SW_BB_DUMP_TRIG_SEL_MASK 0x0000000F //HW module read/write macro #define PHY_READ_REG(addr) SOC_READ_REG(PHY_BASEADDR + addr) #define PHY_WRITE_REG(addr,value) SOC_WRITE_REG(PHY_BASEADDR + addr,value)