//-----------------------------------
#define CFG_GTMR_RVER_ADDR 0x0000
#define GTMR_RF_VER_OFFSET 0
#define GTMR_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_GTMR_CFG_ADDR 0x0004
#define TMR_ENA_CFG_OFFSET 4
#define TMR_ENA_CFG_MASK 0x000000F0
#define TMR_MODE_CFG_OFFSET 0
#define TMR_MODE_CFG_MASK 0x0000000F

//-----------------------------------
#define CFG_GTMR0_CFG_ADDR 0x0008
#define TMR0_CFG_OFFSET 0
#define TMR0_CFG_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GTMR1_CFG_ADDR 0x000C
#define TMR1_CFG_OFFSET 0
#define TMR1_CFG_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GTMR2_CFG_ADDR 0x0010
#define TMR2_CFG_OFFSET 0
#define TMR2_CFG_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GTMR3_CFG_ADDR 0x0014
#define TMR3_CFG_OFFSET 0
#define TMR3_CFG_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GTMR_INT_ENA_ADDR 0x00018
#define TMR_INT_ENA_OFFSET 0
#define TMR_INT_ENA_MASK 0x0000000F

//-----------------------------------
#define CFG_GTMR_INT_STS_ADDR 0x0001c
#define TMR_INT_STS_OFFSET 0
#define TMR_INT_STS_MASK 0x0000000F

//-----------------------------------
#define CFG_GTMR_INT_CLR_ADDR 0x00020
#define TMR_INT_CLR_OFFSET 0
#define TMR_INT_CLR_MASK 0x0000000F

//-----------------------------------
#define CFG_GTMR_INT_RAW_ADDR 0x00024
#define TMR_INT_RAW_OFFSET 0
#define TMR_INT_RAW_MASK 0x0000000F

//-----------------------------------
#define CFG_GTMR0_VAL_ADDR 0x0028
#define TMR0_CNT_OFFSET 0
#define TMR0_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GTMR1_VAL_ADDR 0x002c
#define TMR1_CNT_OFFSET 0
#define TMR1_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GTMR2_VAL_ADDR 0x0030
#define TMR2_CNT_OFFSET 0
#define TMR2_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GTMR3_VAL_ADDR 0x0034
#define TMR3_CNT_OFFSET 0
#define TMR3_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GTMR_CNT_CLR_ADDR 0x0038
#define TMR_CLR_OFFSET 0
#define TMR_CLR_MASK 0x0000000F

//HW module read/write macro
#define GTMR_READ_REG(addr) SOC_READ_REG(GTMR_BASEADDR + addr)
#define GTMR_WRITE_REG(addr,value) SOC_WRITE_REG(GTMR_BASEADDR + addr,value)
#define GTMR1_READ_REG(addr) SOC_READ_REG(GTMR1_BASEADDR + addr)
#define GTMR1_WRITE_REG(addr,value) SOC_WRITE_REG(GTMR1_BASEADDR + addr,value)