//----------------------------------- #define CFG_I2SCONF_ADDR 0x0008 #define REG_BCK_DIV_NUM_OFFSET 22 #define REG_BCK_DIV_NUM_MASK 0x0FC00000 #define REG_CLKM_DIV_NUM_OFFSET 16 #define REG_CLKM_DIV_NUM_MASK 0x003F0000 #define REG_BITS_MOD_OFFSET 12 #define REG_BITS_MOD_MASK 0x0000F000 #define REG_RECE_MSB_SHIFT_OFFSET 11 #define REG_RECE_MSB_SHIFT_MASK 0x00000800 #define REG_TRANS_MSB_SHIFT_OFFSET 10 #define REG_TRANS_MSB_SHIFT_MASK 0x00000400 #define I2S_RX_START_OFFSET 9 #define I2S_RX_START_MASK 0x00000200 #define I2S_TX_START_OFFSET 8 #define I2S_TX_START_MASK 0x00000100 #define REG_MSB_RIGHT_OFFSET 7 #define REG_MSB_RIGHT_MASK 0x00000080 #define REG_RIGHT_FIRST_OFFSET 6 #define REG_RIGHT_FIRST_MASK 0x00000040 #define REG_RECE_SLAVE_MOD_OFFSET 5 #define REG_RECE_SLAVE_MOD_MASK 0x00000020 #define REG_TRANS_SLAVE_MOD_OFFSET 4 #define REG_TRANS_SLAVE_MOD_MASK 0x00000010 #define I2S_RX_FIFO_RESET_OFFSET 3 #define I2S_RX_FIFO_RESET_MASK 0x00000008 #define I2S_TX_FIFO_RESET_OFFSET 2 #define I2S_TX_FIFO_RESET_MASK 0x00000004 #define I2S_RX_RESET_OFFSET 1 #define I2S_RX_RESET_MASK 0x00000002 #define I2S_TX_RESET_OFFSET 0 #define I2S_TX_RESET_MASK 0x00000001 //----------------------------------- #define CFG_I2SINT_RAW_ADDR 0x000C #define I2S_TX_REMPTY_INT_RAW_OFFSET 5 #define I2S_TX_REMPTY_INT_RAW_MASK 0x00000020 #define I2S_TX_WFULL_INT_RAW_OFFSET 4 #define I2S_TX_WFULL_INT_RAW_MASK 0x00000010 #define I2S_RX_REMPTY_INT_RAW_OFFSET 3 #define I2S_RX_REMPTY_INT_RAW_MASK 0x00000008 #define I2S_RX_WFULL_INT_RAW_OFFSET 2 #define I2S_RX_WFULL_INT_RAW_MASK 0x00000004 #define I2S_TX_PUT_DATA_INT_RAW_OFFSET 1 #define I2S_TX_PUT_DATA_INT_RAW_MASK 0x00000002 #define I2S_RX_TAKE_DATA_INT_RAW_OFFSET 0 #define I2S_RX_TAKE_DATA_INT_RAW_MASK 0x00000001 //----------------------------------- #define CFG_I2SINT_ST_ADDR 0x0010 #define I2S_TX_REMPTY_INT_ST_OFFSET 5 #define I2S_TX_REMPTY_INT_ST_MASK 0x00000020 #define I2S_TX_WFULL_INT_ST_OFFSET 4 #define I2S_TX_WFULL_INT_ST_MASK 0x00000010 #define I2S_RX_REMPTY_INT_ST_OFFSET 3 #define I2S_RX_REMPTY_INT_ST_MASK 0x00000008 #define I2S_RX_WFULL_INT_ST_OFFSET 2 #define I2S_RX_WFULL_INT_ST_MASK 0x00000004 #define I2S_TX_PUT_DATA_INT_ST_OFFSET 1 #define I2S_TX_PUT_DATA_INT_ST_MASK 0x00000002 #define I2S_RX_TAKE_DATA_INT_ST_OFFSET 0 #define I2S_RX_TAKE_DATA_INT_ST_MASK 0x00000001 //----------------------------------- #define CFG_I2SINT_ENA_ADDR 0x0014 #define I2S_TX_REMPTY_INT_ENA_OFFSET 5 #define I2S_TX_REMPTY_INT_ENA_MASK 0x00000020 #define I2S_TX_WFULL_INT_ENA_OFFSET 4 #define I2S_TX_WFULL_INT_ENA_MASK 0x00000010 #define I2S_RX_REMPTY_INT_ENA_OFFSET 3 #define I2S_RX_REMPTY_INT_ENA_MASK 0x00000008 #define I2S_RX_WFULL_INT_ENA_OFFSET 2 #define I2S_RX_WFULL_INT_ENA_MASK 0x00000004 #define I2S_TX_PUT_DATA_INT_ENA_OFFSET 1 #define I2S_TX_PUT_DATA_INT_ENA_MASK 0x00000002 #define I2S_RX_TAKE_DATA_INT_ENA_OFFSET 0 #define I2S_RX_TAKE_DATA_INT_ENA_MASK 0x00000001 //----------------------------------- #define CFG_I2SINT_CLR_ADDR 0x0018 #define I2S_TX_REMPTY_INT_CLR_OFFSET 5 #define I2S_TX_REMPTY_INT_CLR_MASK 0x00000020 #define I2S_TX_WFULL_INT_CLR_OFFSET 4 #define I2S_TX_WFULL_INT_CLR_MASK 0x00000010 #define I2S_RX_REMPTY_INT_CLR_OFFSET 3 #define I2S_RX_REMPTY_INT_CLR_MASK 0x00000008 #define I2S_RX_WFULL_INT_CLR_OFFSET 2 #define I2S_RX_WFULL_INT_CLR_MASK 0x00000004 #define I2S_TX_PUT_DATA_INT_CLR_OFFSET 1 #define I2S_TX_PUT_DATA_INT_CLR_MASK 0x00000002 #define I2S_RX_TAKE_DATA_INT_CLR_OFFSET 0 #define I2S_RX_TAKE_DATA_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_I2STIMING_ADDR 0x001C #define REG_TRANS_BCK_IN_INV_OFFSET 22 #define REG_TRANS_BCK_IN_INV_MASK 0x00400000 #define REG_RECE_DSYNC_SW_OFFSET 21 #define REG_RECE_DSYNC_SW_MASK 0x00200000 #define REG_TRANS_DSYNC_SW_OFFSET 20 #define REG_TRANS_DSYNC_SW_MASK 0x00100000 #define REG_RECE_BCK_OUT_DELAY_OFFSET 18 #define REG_RECE_BCK_OUT_DELAY_MASK 0x000C0000 #define REG_RECE_WS_OUT_DELAY_OFFSET 16 #define REG_RECE_WS_OUT_DELAY_MASK 0x00030000 #define REG_TRANS_SD_OUT_DELAY_OFFSET 14 #define REG_TRANS_SD_OUT_DELAY_MASK 0x0000C000 #define REG_TRANS_WS_OUT_DELAY_OFFSET 12 #define REG_TRANS_WS_OUT_DELAY_MASK 0x00003000 #define REG_TRANS_BCK_OUT_DELAY_OFFSET 10 #define REG_TRANS_BCK_OUT_DELAY_MASK 0x00000C00 #define REG_RECE_SD_IN_DELAY_OFFSET 8 #define REG_RECE_SD_IN_DELAY_MASK 0x00000300 #define REG_RECE_WS_IN_DELAY_OFFSET 6 #define REG_RECE_WS_IN_DELAY_MASK 0x000000C0 #define REG_RECE_BCK_IN_DELAY_OFFSET 4 #define REG_RECE_BCK_IN_DELAY_MASK 0x00000030 #define REG_TRANS_WS_IN_DELAY_OFFSET 2 #define REG_TRANS_WS_IN_DELAY_MASK 0x0000000C #define REG_TRANS_BCK_IN_DELAY_OFFSET 0 #define REG_TRANS_BCK_IN_DELAY_MASK 0x00000003 //----------------------------------- #define CFG_I2S_FIFO_CONF_ADDR 0x0020 #define REG_I2S_RX_FIFO_MOD_OFFSET 16 #define REG_I2S_RX_FIFO_MOD_MASK 0x00070000 #define REG_I2S_TX_FIFO_MOD_OFFSET 13 #define REG_I2S_TX_FIFO_MOD_MASK 0x0000E000 #define REG_I2S_DSCR_EN_OFFSET 12 #define REG_I2S_DSCR_EN_MASK 0x00001000 #define REG_I2S_TX_DATA_NUM_OFFSET 6 #define REG_I2S_TX_DATA_NUM_MASK 0x00000FC0 #define REG_I2S_RX_DATA_NUM_OFFSET 0 #define REG_I2S_RX_DATA_NUM_MASK 0x0000003F //----------------------------------- #define CFG_I2SRXEOF_NUM_ADDR 0x0024 #define REG_I2S_RX_EOF_NUM_OFFSET 0 #define REG_I2S_RX_EOF_NUM_MASK 0xFFFFFFFF //----------------------------------- #define CFG_I2SCONF_SIGLE_DATA_ADDR 0x0028 #define REG_I2S_SIGLE_DATA_OFFSET 0 #define REG_I2S_SIGLE_DATA_MASK 0xFFFFFFFF //----------------------------------- #define CFG_I2SCONF_CHAN_ADDR 0x002C #define REG_RX_CHAN_MOD_OFFSET 3 #define REG_RX_CHAN_MOD_MASK 0x00000018 #define REG_TX_CHAN_MOD_OFFSET 0 #define REG_TX_CHAN_MOD_MASK 0x00000007 //HW module read/write macro #define I2S_READ_REG(addr) SOC_READ_REG(I2S_BASEADDR + addr) #define I2S_WRITE_REG(addr,value) SOC_WRITE_REG(I2S_BASEADDR + addr,value)