//----------------------------------- #define CFG_RAW_DATA_MODE_ADDR 0x0000 #define CFG_RX_RAW_DATA_MODE_OFFSET 0 #define CFG_RX_RAW_DATA_MODE_MASK 0x00000001 //----------------------------------- #define CFG_RAW_INT_ENA_ADDR 0x0004 #define CFG_RAW_INT_ENABLE_OFFSET 0 #define CFG_RAW_INT_ENABLE_MASK 0x0000000F //----------------------------------- #define CFG_RAW_INT_STATUS_ADDR 0x0008 #define RO_RAW_INT_STATUS_OFFSET 0 #define RO_RAW_INT_STATUS_MASK 0x0000000F //----------------------------------- #define CFG_RAW_INT_CLR_ADDR 0x000c #define CFG_RAW_INT_CLR_3_OFFSET 3 #define CFG_RAW_INT_CLR_3_MASK 0x00000008 #define CFG_RAW_INT_CLR_2_OFFSET 2 #define CFG_RAW_INT_CLR_2_MASK 0x00000004 #define CFG_RAW_INT_CLR_1_OFFSET 1 #define CFG_RAW_INT_CLR_1_MASK 0x00000002 #define CFG_RAW_INT_CLR_0_OFFSET 0 #define CFG_RAW_INT_CLR_0_MASK 0x00000001 //----------------------------------- #define CFG_RAW_INT_PRI0_MASK_ADDR 0x0010 #define CFG_RAW_INT_PRI0_MASK_OFFSET 0 #define CFG_RAW_INT_PRI0_MASK_MASK 0x0000000F //----------------------------------- #define CFG_RAW_INT_PRI1_MASK_ADDR 0x0014 #define CFG_RAW_INT_PRI1_MASK_OFFSET 0 #define CFG_RAW_INT_PRI1_MASK_MASK 0x0000000F //----------------------------------- #define CFG_RAW_INT_PRI2_MASK_ADDR 0x0018 #define CFG_RAW_INT_PRI2_MASK_OFFSET 0 #define CFG_RAW_INT_PRI2_MASK_MASK 0x0000000F //----------------------------------- #define CFG_RAW_INT_PRI3_MASK_ADDR 0x0020 #define CFG_RAW_INT_PRI3_MASK_OFFSET 0 #define CFG_RAW_INT_PRI3_MASK_MASK 0x0000000F //----------------------------------- #define CFG_TX_RAW_FC_0_ADDR 0x0024 #define RO_TX_RAW_FC_0_OFFSET 0 #define RO_TX_RAW_FC_0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_TX_RAW_FC_1_ADDR 0x0028 #define RO_TX_RAW_FC_1_OFFSET 0 #define RO_TX_RAW_FC_1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_TX_RAW_FC_2_ADDR 0x002c #define RO_TX_RAW_FC_2_OFFSET 0 #define RO_TX_RAW_FC_2_MASK 0xFFFFFFFF //----------------------------------- #define CFG_TX_RAW_FC_3_ADDR 0x0030 #define RO_TX_RAW_FC_3_OFFSET 0 #define RO_TX_RAW_FC_3_MASK 0xFFFFFFFF //----------------------------------- #define CFG_TX_SW_FC_0_ADDR 0x0034 #define CFG_TX_SW_FC_0_OFFSET 0 #define CFG_TX_SW_FC_0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_TX_SW_FC_1_ADDR 0x0038 #define CFG_TX_SW_FC_1_OFFSET 0 #define CFG_TX_SW_FC_1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_TX_SW_FC_2_ADDR 0x003c #define CFG_TX_SW_FC_2_OFFSET 0 #define CFG_TX_SW_FC_2_MASK 0xFFFFFFFF //----------------------------------- #define CFG_TX_SW_FC_3_ADDR 0x0040 #define CFG_TX_SW_FC_3_OFFSET 0 #define CFG_TX_SW_FC_3_MASK 0xFFFFFFFF //----------------------------------- #define CFG_SW_FC_VALID_ADDR 0x0044 #define CFG_SW_FC_VALID_OFFSET 0 #define CFG_SW_FC_VALID_MASK 0x00000001 //----------------------------------- #define CFG_SW_TX_PROTO_ADDR 0x0048 #define CFG_SW_TX_PROTO_OFFSET 0 #define CFG_SW_TX_PROTO_MASK 0x00000007 //----------------------------------- #define CFG_RAW_NTB_TIMER_ADDR 0x004c #define RAW_NTB_TIMER_OFFSET 0 #define RAW_NTB_TIMER_MASK 0xFFFFFFFF //----------------------------------- #define CFG_TX_FC_DATA0_ADDR 0x0050 #define CFG_TX_FC_DATA0_OFFSET 0 #define CFG_TX_FC_DATA0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_TX_FC_DATA1_ADDR 0x0054 #define CFG_TX_FC_DATA1_OFFSET 0 #define CFG_TX_FC_DATA1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_TX_FC_DATA2_ADDR 0x0058 #define CFG_TX_FC_DATA2_OFFSET 0 #define CFG_TX_FC_DATA2_MASK 0xFFFFFFFF //----------------------------------- #define CFG_TX_FC_DATA3_ADDR 0x005c #define CFG_TX_FC_DATA3_OFFSET 0 #define CFG_TX_FC_DATA3_MASK 0xFFFFFFFF //----------------------------------- #define CFG_TX_FC_NEED_UPD_ADDR 0x0060 #define CFG_TX_FC_NEED_UPD_OFFSET 0 #define CFG_TX_FC_NEED_UPD_MASK 0x00000001 //----------------------------------- #define CFG_TX_FC_PARSER_FORCE_ADDR 0x0064 #define CFG_TX_RESP_EXP_FORCE_EN_OFFSET 23 #define CFG_TX_RESP_EXP_FORCE_EN_MASK 0x00800000 #define CFG_TX_RESP_EXP_OFFSET 22 #define CFG_TX_RESP_EXP_MASK 0x00400000 #define CFG_TX_RESP_DT_FORCE_EN_OFFSET 21 #define CFG_TX_RESP_DT_FORCE_EN_MASK 0x00200000 #define CFG_TX_RESP_DT_OFFSET 17 #define CFG_TX_RESP_DT_MASK 0x001E0000 #define CFG_TX_PBH_LEN_FORCE_EN_OFFSET 16 #define CFG_TX_PBH_LEN_FORCE_EN_MASK 0x00010000 #define CFG_TX_PBH_LEN_OFFSET 13 #define CFG_TX_PBH_LEN_MASK 0x0000E000 #define CFG_TX_SHORT_MPDU_FORCE_EN_OFFSET 12 #define CFG_TX_SHORT_MPDU_FORCE_EN_MASK 0x00001000 #define CFG_TX_SHORT_MPDU_OFFSET 11 #define CFG_TX_SHORT_MPDU_MASK 0x00000800 #define CFG_TX_PBSIZE_FORCE_EN_OFFSET 10 #define CFG_TX_PBSIZE_FORCE_EN_MASK 0x00000400 #define CFG_TX_PBSIZE_OFFSET 8 #define CFG_TX_PBSIZE_MASK 0x00000300 #define CFG_TX_TMI_FORCE_EN_OFFSET 7 #define CFG_TX_TMI_FORCE_EN_MASK 0x00000080 #define CFG_TX_TMI_OFFSET 2 #define CFG_TX_TMI_MASK 0x0000007C #define CFG_TX_DTEI_BCMC_FORCE_EN_OFFSET 1 #define CFG_TX_DTEI_BCMC_FORCE_EN_MASK 0x00000002 #define CFG_TX_DTEI_BCMC_OFFSET 0 #define CFG_TX_DTEI_BCMC_MASK 0x00000001 //----------------------------------- #define CFG_RAW_DUMMY_0_ADDR 0x0068 //----------------------------------- #define CFG_RX_FC_PARSER_FORCE_0_ADDR 0x006c #define CFG_RX_NEED_RESP_SOUND_ACK_FORCE_EN_OFFSET 31 #define CFG_RX_NEED_RESP_SOUND_ACK_FORCE_EN_MASK 0x80000000 #define CFG_RX_NEED_RESP_SOUND_ACK_OFFSET 30 #define CFG_RX_NEED_RESP_SOUND_ACK_MASK 0x40000000 #define CFG_RX_NEED_RESP_CTS_FORCE_EN_OFFSET 29 #define CFG_RX_NEED_RESP_CTS_FORCE_EN_MASK 0x20000000 #define CFG_RX_NEED_RESP_CTS_OFFSET 28 #define CFG_RX_NEED_RESP_CTS_MASK 0x10000000 #define CFG_RX_NEED_RESP_SACK_FORCE_EN_OFFSET 27 #define CFG_RX_NEED_RESP_SACK_FORCE_EN_MASK 0x08000000 #define CFG_RX_NEED_RESP_SACK_OFFSET 26 #define CFG_RX_NEED_RESP_SACK_MASK 0x04000000 #define CFG_RX_LONG_MPDU_FORCE_EN_OFFSET 25 #define CFG_RX_LONG_MPDU_FORCE_EN_MASK 0x02000000 #define CFG_RX_LONG_MPDU_OFFSET 24 #define CFG_RX_LONG_MPDU_MASK 0x01000000 #define CFG_RX_SHORT_MPDU_FORCE_EN_OFFSET 23 #define CFG_RX_SHORT_MPDU_FORCE_EN_MASK 0x00800000 #define CFG_RX_SHORT_MPDU_OFFSET 22 #define CFG_RX_SHORT_MPDU_MASK 0x00400000 #define CFG_RX_DTEI_MCBC_FORCE_EN_OFFSET 21 #define CFG_RX_DTEI_MCBC_FORCE_EN_MASK 0x00200000 #define CFG_RX_DTEI_MCBC_OFFSET 20 #define CFG_RX_DTEI_MCBC_MASK 0x00100000 #define CFG_RX_PHASE_FORCE_EN_OFFSET 19 #define CFG_RX_PHASE_FORCE_EN_MASK 0x00080000 #define CFG_RX_PHASE_OFFSET 17 #define CFG_RX_PHASE_MASK 0x00060000 #define CFG_RX_FC_FL_FORCE_EN_OFFSET 16 #define CFG_RX_FC_FL_FORCE_EN_MASK 0x00010000 #define CFG_RX_FC_FL_FORCE_OFFSET 0 #define CFG_RX_FC_FL_FORCE_MASK 0x0000FFFF //----------------------------------- #define CFG_RX_FC_PARSER_FORCE_1_ADDR 0x0070 #define CFG_RX_PBSIZE_FORCE_EN_OFFSET 26 #define CFG_RX_PBSIZE_FORCE_EN_MASK 0x04000000 #define CFG_RX_PBSIZE_OFFSET 23 #define CFG_RX_PBSIZE_MASK 0x03800000 #define CFG_RX_PBNUM_FORCE_EN_OFFSET 22 #define CFG_RX_PBNUM_FORCE_EN_MASK 0x00400000 #define CFG_RX_PBNUM_OFFSET 19 #define CFG_RX_PBNUM_MASK 0x00380000 #define CFG_RX_SACK_BITMAP_FORCE_EN_OFFSET 18 #define CFG_RX_SACK_BITMAP_FORCE_EN_MASK 0x00040000 #define CFG_RX_SACK_BITMAP_OFFSET 14 #define CFG_RX_SACK_BITMAP_MASK 0x0003C000 #define CFG_RX_TMI_FORCE_EN_OFFSET 13 #define CFG_RX_TMI_FORCE_EN_MASK 0x00002000 #define CFG_RX_TMI_OFFSET 8 #define CFG_RX_TMI_MASK 0x00001F00 #define CFG_RX_PBCRC_LEN_FORCE_EN_OFFSET 7 #define CFG_RX_PBCRC_LEN_FORCE_EN_MASK 0x00000080 #define CFG_RX_PBCRC_LEN_OFFSET 4 #define CFG_RX_PBCRC_LEN_MASK 0x00000070 #define CFG_RX_PBH_LEN_FORCE_EN_OFFSET 3 #define CFG_RX_PBH_LEN_FORCE_EN_MASK 0x00000008 #define CFG_RX_PBH_LEN_OFFSET 0 #define CFG_RX_PBH_LEN_MASK 0x00000007 //HW module read/write macro #define RGF_RAW_READ_REG(addr) SOC_READ_REG(RGF_RAW_BASEADDR + addr) #define RGF_RAW_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_RAW_BASEADDR + addr,value)