//-----------------------------------
#define CFG_SEC_RVER_ADDR 0x0000
#define SEC_RF_VER_OFFSET 0
#define SEC_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SEC_GLB_ENA_ADDR 0x0004
#define RV5_CORE1_EB_OFFSET 6
#define RV5_CORE1_EB_MASK 0x00000040
#define INTC1_EB_OFFSET 5
#define INTC1_EB_MASK 0x00000020
#define WDG1_EB_OFFSET 4
#define WDG1_EB_MASK 0x00000010
#define GTMR1_EB_OFFSET 3
#define GTMR1_EB_MASK 0x00000008
#define EFUSE_EB_OFFSET 2
#define EFUSE_EB_MASK 0x00000004
#define SEC_EB_OFFSET 1
#define SEC_EB_MASK 0x00000002
#define EMC_EB_OFFSET 0
#define EMC_EB_MASK 0x00000001

//-----------------------------------
#define CFG_SEC_GLB_RST_ADDR 0x0008
#define CHIP_SOFT_RST_OFFSET 7
#define CHIP_SOFT_RST_MASK 0x00000080
#define RV5_CORE1_SOFT_RST_P_OFFSET 6
#define RV5_CORE1_SOFT_RST_P_MASK 0x00000040
#define INTC1_SOFT_RST_OFFSET 5
#define INTC1_SOFT_RST_MASK 0x00000020
#define WDG1_SOFT_RST_OFFSET 4
#define WDG1_SOFT_RST_MASK 0x00000010
#define GTMR1_SOFT_RST_OFFSET 3
#define GTMR1_SOFT_RST_MASK 0x00000008
#define EFUSE_SOFT_RST_OFFSET 2
#define EFUSE_SOFT_RST_MASK 0x00000004
#define SEC_SOFT_RST_OFFSET 1
#define SEC_SOFT_RST_MASK 0x00000002
#define EMC_SOFT_RST_OFFSET 0
#define EMC_SOFT_RST_MASK 0x00000001

//-----------------------------------
#define CFG_CPU1_START_PC_ADDR 0x004c
#define CORE1_START_PC_OFFSET 0
#define CORE1_START_PC_MASK 0xFFFFFFFF

//HW module read/write macro
#define SEC_GLB_RF_READ_REG(addr) SOC_READ_REG(SEC_GLB_RF_BASEADDR + addr)
#define SEC_GLB_RF_WRITE_REG(addr,value) SOC_WRITE_REG(SEC_GLB_RF_BASEADDR + addr,value)