//-----------------------------------
#define CFG_AHB_BUSMON_RVER_ADDR 0x0000
#define AHB_BUSMON_RF_VER_OFFSET 0
#define AHB_BUSMON_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_BUSMON_CFG_ADDR 0x0004
#define BUSMON_INIT_OFFSET 31
#define BUSMON_INIT_MASK 0x80000000
#define RD_WR_MON_OFFSET 3
#define RD_WR_MON_MASK 0x00000018
#define MON_CHNL_OFFSET 0
#define MON_CHNL_MASK 0x00000007

//-----------------------------------
#define CFG_TRANS_MON_OPT_ADDR 0x0008
#define MON_SIZE_OFFSET 16
#define MON_SIZE_MASK 0x00070000
#define MON_BURST_OFFSET 0
#define MON_BURST_MASK 0x00000007

//-----------------------------------
#define CFG_MON_ADDR_LOW_ADDR 0x000C
#define MON_ADDR_L_OFFSET 0
#define MON_ADDR_L_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MON_ADDR_HIGH_ADDR 0x0010
#define MON_ADDR_H_OFFSET 0
#define MON_ADDR_H_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BUSMON_TYPE_ENA_ADDR 0x0014
#define ADDR_MON_REV_OFFSET 8
#define ADDR_MON_REV_MASK 0x00000100
#define SIZE_MON_ENA_OFFSET 2
#define SIZE_MON_ENA_MASK 0x00000004
#define BURST_MON_ENA_OFFSET 1
#define BURST_MON_ENA_MASK 0x00000002
#define ADDR_MON_ENA_OFFSET 0
#define ADDR_MON_ENA_MASK 0x00000001

//-----------------------------------
#define CFG_BUSMON_INT_CLR_ADDR 0x0018
#define TRANS_MON_INT_CLR_OFFSET 0
#define TRANS_MON_INT_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_CAPTURE_CMD_ADDR 0x001C
#define CAP_HWRITE_OFFSET 6
#define CAP_HWRITE_MASK 0x00000040
#define CAP_HSIZE_OFFSET 3
#define CAP_HSIZE_MASK 0x00000038
#define CAP_HBURST_OFFSET 0
#define CAP_HBURST_MASK 0x00000007

//-----------------------------------
#define CFG_CAPTURE_HADDR_ADDR 0x0020
#define CAP_HADDR_OFFSET 0
#define CAP_HADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CAPTURE_HDATA_0_ADDR 0x0024
#define CAP_HDATA_0_OFFSET 0
#define CAP_HDATA_0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CAPTURE_HDATA_1_ADDR 0x0028
#define CAP_HDATA_1_OFFSET 0
#define CAP_HDATA_1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CAPTURE_HDATA_2_ADDR 0x002C
#define CAP_HDATA_2_OFFSET 0
#define CAP_HDATA_2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CAPTURE_HDATA_3_ADDR 0x0030
#define CAP_HDATA_3_OFFSET 0
#define CAP_HDATA_3_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CAPTURE_HDATA_4_ADDR 0x0034
#define CAP_HDATA_4_OFFSET 0
#define CAP_HDATA_4_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CAPTURE_HDATA_5_ADDR 0x0038
#define CAP_HDATA_5_OFFSET 0
#define CAP_HDATA_5_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CAPTURE_HDATA_6_ADDR 0x003C
#define CAP_HDATA_6_OFFSET 0
#define CAP_HDATA_6_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CAPTURE_HDATA_7_ADDR 0x0040
#define CAP_HDATA_7_OFFSET 0
#define CAP_HDATA_7_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CAPTURE_HDATA_8_ADDR 0x0044
#define CAP_HDATA_8_OFFSET 0
#define CAP_HDATA_8_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CAPTURE_HDATA_9_ADDR 0x0048
#define CAP_HDATA_9_OFFSET 0
#define CAP_HDATA_9_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CAPTURE_HDATA_10_ADDR 0x004C
#define CAP_HDATA_10_OFFSET 0
#define CAP_HDATA_10_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CAPTURE_HDATA_11_ADDR 0x0050
#define CAP_HDATA_11_OFFSET 0
#define CAP_HDATA_11_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CAPTURE_HDATA_12_ADDR 0x0054
#define CAP_HDATA_12_OFFSET 0
#define CAP_HDATA_12_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CAPTURE_HDATA_13_ADDR 0x0058
#define CAP_HDATA_13_OFFSET 0
#define CAP_HDATA_13_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CAPTURE_HDATA_14_ADDR 0x005C
#define CAP_HDATA_14_OFFSET 0
#define CAP_HDATA_14_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CAPTURE_HDATA_15_ADDR 0x0060
#define CAP_HDATA_15_OFFSET 0
#define CAP_HDATA_15_MASK 0xFFFFFFFF

//HW module read/write macro
#define AHB_BUSMON0_READ_REG(addr) SOC_READ_REG(AHB_BUSMON0_BASEADDR + addr)
#define AHB_BUSMON0_WRITE_REG(addr,value) SOC_WRITE_REG(AHB_BUSMON0_BASEADDR + addr,value)
#define AHB_BUSMON1_READ_REG(addr) SOC_READ_REG(AHB_BUSMON1_BASEADDR + addr)
#define AHB_BUSMON1_WRITE_REG(addr,value) SOC_WRITE_REG(AHB_BUSMON1_BASEADDR + addr,value)
#define AHB_BUSMON2_READ_REG(addr) SOC_READ_REG(AHB_BUSMON2_BASEADDR + addr)
#define AHB_BUSMON2_WRITE_REG(addr,value) SOC_WRITE_REG(AHB_BUSMON2_BASEADDR + addr,value)