//-----------------------------------
#define CFG_ANA_DIG_REG_CFG0_ADDR 0x0

//-----------------------------------
#define CFG_ANA_DIG_REG_CFG1_ADDR 0x4
#define MPRX0_SEL_CLK01_OFFSET 31
#define MPRX0_SEL_CLK01_MASK 0x80000000
#define MPRX1_SEL_CLK01_OFFSET 30
#define MPRX1_SEL_CLK01_MASK 0x40000000

//-----------------------------------
#define CFG_ANA_DIG_REG_CFG2_ADDR 0x8
#define MIPITX_LDO_EN_OFFSET 31
#define MIPITX_LDO_EN_MASK 0x80000000
#define MIPITX_RESETB_OFFSET 30
#define MIPITX_RESETB_MASK 0x40000000

//-----------------------------------
#define CFG_ANA_DIG_REG_CFG3_ADDR 0xc
#define MIPIPLL_REF_SEL_DIV2_OFFSET 31
#define MIPIPLL_REF_SEL_DIV2_MASK 0x80000000
#define MIPIPLL_MMDIV_SEL_OFFSET 23
#define MIPIPLL_MMDIV_SEL_MASK 0x7F800000
#define MIPIPLL_LPF_C2_SEL_OFFSET 19
#define MIPIPLL_LPF_C2_SEL_MASK 0x00180000
#define MIPIPLL_LPF_RES_SEL_OFFSET 11
#define MIPIPLL_LPF_RES_SEL_MASK 0x0001F800
#define MIPIPLL_CP_SEL_OFFSET 7
#define MIPIPLL_CP_SEL_MASK 0x00000180
#define MIPIPLL_VCO_FAST_OFFSET 6
#define MIPIPLL_VCO_FAST_MASK 0x00000040
#define MIPIPLL_VCO_SLOW_OFFSET 5
#define MIPIPLL_VCO_SLOW_MASK 0x00000020
#define MIPIPLL_CMLBUF_IBSEL_OFFSET 1
#define MIPIPLL_CMLBUF_IBSEL_MASK 0x00000006

//-----------------------------------
#define CFG_ANA_DIG_REG_CFG4_ADDR 0x10
#define MIPIPLL_CML2CMS_IBSEL_OFFSET 28
#define MIPIPLL_CML2CMS_IBSEL_MASK 0x30000000
#define MIPIPLL_CMLDIV2_IBSEL_OFFSET 24
#define MIPIPLL_CMLDIV2_IBSEL_MASK 0x03000000
#define MIPIPLL_DB_CRRNT_SEL_OFFSET 23
#define MIPIPLL_DB_CRRNT_SEL_MASK 0x00800000
#define MIPIPLL_VCO_AMP_OFFSET 19
#define MIPIPLL_VCO_AMP_MASK 0x00780000
#define MIPIPLL_VCO_TMPP_OFFSET 11
#define MIPIPLL_VCO_TMPP_MASK 0x0001F800
#define MIPIPLL_VCO_TMP_OFFSET 3
#define MIPIPLL_VCO_TMP_MASK 0x000001F8
#define MIPIPLL_TX_750M_SEL_OFFSET 2
#define MIPIPLL_TX_750M_SEL_MASK 0x00000004
#define MIPIPLL_RGMII_EN_OFFSET 1
#define MIPIPLL_RGMII_EN_MASK 0x00000002
#define MIPIPLL_AUDIO_EN_OFFSET 0
#define MIPIPLL_AUDIO_EN_MASK 0x00000001

//-----------------------------------
#define CFG_ANA_DIG_REG_CFG5_ADDR 0x14
#define MIPIPLL_SOC_EN_OFFSET 31
#define MIPIPLL_SOC_EN_MASK 0x80000000
#define MIPIPLL_TXMIPI_EN_OFFSET 30
#define MIPIPLL_TXMIPI_EN_MASK 0x40000000
#define MIPIPLL_INDIC_EN_OFFSET 29
#define MIPIPLL_INDIC_EN_MASK 0x20000000
#define MIPIPLL_LCKDT_EN_OFFSET 28
#define MIPIPLL_LCKDT_EN_MASK 0x10000000
#define MIPIPLL_EN_OFFSET 27
#define MIPIPLL_EN_MASK 0x08000000
#define MIPIPLL_ATB_OFFSET 23
#define MIPIPLL_ATB_MASK 0x01800000

//-----------------------------------
#define CFG_ANA_DIG_REG_CFG6_ADDR 0x18
#define MIPIPLL_REFCLK_SEL_OFFSET 31
#define MIPIPLL_REFCLK_SEL_MASK 0x80000000
#define PHYPLL_REFCLK_SEL_OFFSET 30
#define PHYPLL_REFCLK_SEL_MASK 0x40000000

//-----------------------------------
#define CFG_ANA_DIG_REG_CFG7_ADDR 0x1c
#define PLL_EN_OFFSET 31
#define PLL_EN_MASK 0x80000000
#define PLL_INDIC_EN_OFFSET 30
#define PLL_INDIC_EN_MASK 0x40000000
#define PLL_ATB_OFFSET 26
#define PLL_ATB_MASK 0x0C000000
#define PLL_REF_SEL_DIV2_OFFSET 25
#define PLL_REF_SEL_DIV2_MASK 0x02000000
#define PLL_MMDIV_SEL_OFFSET 17
#define PLL_MMDIV_SEL_MASK 0x01FE0000
#define PLL_LCKDT_EN_OFFSET 16
#define PLL_LCKDT_EN_MASK 0x00010000
#define PLL_LPF_C2_SEL_OFFSET 12
#define PLL_LPF_C2_SEL_MASK 0x00003000
#define PLL_LPF_RES_SEL_OFFSET 4
#define PLL_LPF_RES_SEL_MASK 0x000003F0
#define PLL_CP_SEL_OFFSET 0
#define PLL_CP_SEL_MASK 0x00000003

//-----------------------------------
#define CFG_ANA_DIG_REG_CFG8_ADDR 0x20
#define PLL_VCO_FAST_OFFSET 31
#define PLL_VCO_FAST_MASK 0x80000000
#define PLL_VCO_SLOW_OFFSET 30
#define PLL_VCO_SLOW_MASK 0x40000000
#define PLL_CMLBUF_IBSEL_OFFSET 26
#define PLL_CMLBUF_IBSEL_MASK 0x0C000000
#define PLL_CMLCMS_IBSEL_OFFSET 22
#define PLL_CMLCMS_IBSEL_MASK 0x00C00000
#define PLL_CMLDIV2_IBSEL_OFFSET 18
#define PLL_CMLDIV2_IBSEL_MASK 0x000C0000
#define PLL_DB_CRRNT_SEL_OFFSET 17
#define PLL_DB_CRRNT_SEL_MASK 0x00020000
#define PLL_VCO_AMP_OFFSET 13
#define PLL_VCO_AMP_MASK 0x0001E000
#define PLC_PHY_EN_OFFSET 12
#define PLC_PHY_EN_MASK 0x00001000
#define PLL_SOC_CLK_EN_OFFSET 11
#define PLL_SOC_CLK_EN_MASK 0x00000800
#define PLL_DDR_CLK_EN_OFFSET 10
#define PLL_DDR_CLK_EN_MASK 0x00000400
#define PLL_SOC_CLK_SEL_OFFSET 6
#define PLL_SOC_CLK_SEL_MASK 0x000000C0
#define PLL_DDR_CLK_SEL_OFFSET 2
#define PLL_DDR_CLK_SEL_MASK 0x0000000C

//-----------------------------------
#define CFG_ANA_DIG_REG_CFG9_ADDR 0x24
#define PLL_VCO_TMPP_OFFSET 24
#define PLL_VCO_TMPP_MASK 0x3F000000
#define PLL_VCO_TMP_OFFSET 16
#define PLL_VCO_TMP_MASK 0x003F0000

//-----------------------------------
#define CFG_ANA_DIG_REG_CFG10_ADDR 0x28
#define RT_CHNL_DDR_DRV_OFFSET 28
#define RT_CHNL_DDR_DRV_MASK 0x30000000
#define RT_CHNL_MIPI_DRV_OFFSET 24
#define RT_CHNL_MIPI_DRV_MASK 0x03000000

//-----------------------------------
#define CFG_ANA_DIG_REG_CFG11_ADDR 0x2c
#define BG_DCDC_TRIM_OFFSET 28
#define BG_DCDC_TRIM_MASK 0x70000000
#define BG_IC_TEST_SEL_OFFSET 20
#define BG_IC_TEST_SEL_MASK 0x0FF00000
#define BG_ICAL_EN_OFFSET 19
#define BG_ICAL_EN_MASK 0x00080000
#define BG_ICCAL_OFFSET 11
#define BG_ICCAL_MASK 0x0000F800

//-----------------------------------
#define CFG_ANA_DIG_REG_CFG12_ADDR 0x30
#define BG_IR25U_NCH_ADJ_BIT0_OFFSET 20
#define BG_IR25U_NCH_ADJ_BIT0_MASK 0x7FF00000
#define BG_IR25U_NCH_ADJ_BIT1_OFFSET 8
#define BG_IR25U_NCH_ADJ_BIT1_MASK 0x0007FF00
#define BG_IR_TEST_SEL_OFFSET 0
#define BG_IR_TEST_SEL_MASK 0x0000007F

//-----------------------------------
#define CFG_ANA_DIG_REG_CFG13_ADDR 0x34
#define BG_METERADCREF_TRIM_OFFSET 28
#define BG_METERADCREF_TRIM_MASK 0x70000000
#define BG_VBG_TEST_EN_OFFSET 27
#define BG_VBG_TEST_EN_MASK 0x08000000
#define BG_VBG_TEST_SEL_OFFSET 26
#define BG_VBG_TEST_SEL_MASK 0x04000000

//HW module read/write macro
#define ANA_DIG_WRAP_RF_READ_REG(addr) SOC_READ_REG(ANA_DIG_WRAP_RF_BASEADDR + addr)
#define ANA_DIG_WRAP_RF_WRITE_REG(addr,value) SOC_WRITE_REG(ANA_DIG_WRAP_RF_BASEADDR + addr,value)