//-----------------------------------
#define CFG_ANA_PMU_REG_CFG0_ADDR 0x0
#define MADC_CLK_SEL_OFFSET 28
#define MADC_CLK_SEL_MASK 0x30000000
#define XTAL_CRRNT_SEL_OFFSET 20
#define XTAL_CRRNT_SEL_MASK 0x03F00000
#define XTAL_RTUNE_OFFSET 16
#define XTAL_RTUNE_MASK 0x00070000
#define PD_XTAL_OFFSET 15
#define PD_XTAL_MASK 0x00008000
#define BPLL_ATB_EN_OFFSET 14
#define BPLL_ATB_EN_MASK 0x00004000
#define MIPIPLL_ATB_EN_OFFSET 13
#define MIPIPLL_ATB_EN_MASK 0x00002000

//-----------------------------------
#define CFG_ANA_PMU_REG_CFG1_ADDR 0x4
#define GRANITE2_REG_RSV_OFFSET 0
#define GRANITE2_REG_RSV_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_ANA_PMU_REG_CFG2_ADDR 0x8
#define DCDC_VREF_TUNE_OFFSET 28
#define DCDC_VREF_TUNE_MASK 0xF0000000
#define OVR_STRESS_FLAG_OFFSET 27
#define OVR_STRESS_FLAG_MASK 0x08000000
#define GPIO_M_DIGEN_OFFSET 15
#define GPIO_M_DIGEN_MASK 0x03FF8000
#define GPIO_REFCM_DIGEN_OFFSET 11
#define GPIO_REFCM_DIGEN_MASK 0x00001800

//-----------------------------------
#define CFG_ANA_PMU_REG_CFG3_ADDR 0xc
#define METER_ADC_PD_CH1_OFFSET 31
#define METER_ADC_PD_CH1_MASK 0x80000000
#define METER_BPROG_CH1_OFFSET 27
#define METER_BPROG_CH1_MASK 0x38000000
#define METER_ADC_CLK_DIV_CH1_OFFSET 23
#define METER_ADC_CLK_DIV_CH1_MASK 0x01800000
#define METER_ADC_PD_CH2_OFFSET 22
#define METER_ADC_PD_CH2_MASK 0x00400000
#define METER_BPROG_CH2_OFFSET 18
#define METER_BPROG_CH2_MASK 0x001C0000
#define METER_ADC_CLK_DIV_CH2_OFFSET 14
#define METER_ADC_CLK_DIV_CH2_MASK 0x0000C000
#define METER_ADC_BIAS_INT1A_CTL_OFFSET 10
#define METER_ADC_BIAS_INT1A_CTL_MASK 0x00000C00
#define METER_ADC_BIAS_INT1B_CTL_OFFSET 6
#define METER_ADC_BIAS_INT1B_CTL_MASK 0x000000C0
#define METER_ADC_BIAS_INT2_CTL_OFFSET 2
#define METER_ADC_BIAS_INT2_CTL_MASK 0x0000000C

//-----------------------------------
#define CFG_ANA_PMU_REG_CFG4_ADDR 0x10
#define METER_ADC_BIAS_INT3_CTL_OFFSET 28
#define METER_ADC_BIAS_INT3_CTL_MASK 0x30000000
#define METER_ADC_BIAS_VCM_CTL_OFFSET 24
#define METER_ADC_BIAS_VCM_CTL_MASK 0x03000000
#define METER_ADC_BIAS_VREFP_CTL_OFFSET 20
#define METER_ADC_BIAS_VREFP_CTL_MASK 0x00300000

//-----------------------------------
#define CFG_ANA_PMU_REG_CFG5_ADDR 0x14
#define METER_BG_BG_CA_OFFSET 24
#define METER_BG_BG_CA_MASK 0x1F000000
#define METER_BG_BG_CB_OFFSET 16
#define METER_BG_BG_CB_MASK 0x001F0000
#define METER_BG_BYP_R_OFFSET 15
#define METER_BG_BYP_R_MASK 0x00008000
#define METER_BG_CORE_CA_OFFSET 7
#define METER_BG_CORE_CA_MASK 0x00000F80

//-----------------------------------
#define CFG_ANA_PMU_REG_CFG6_ADDR 0x18
#define METER_BG_CORE_CB_OFFSET 24
#define METER_BG_CORE_CB_MASK 0x1F000000
#define METER_BG_CUR_CTL_OFFSET 20
#define METER_BG_CUR_CTL_MASK 0x00700000
#define METER_BG_PD_CLK_OFFSET 19
#define METER_BG_PD_CLK_MASK 0x00080000
#define METER_ECG_LDOFFN_DET_OFFSET 18
#define METER_ECG_LDOFFN_DET_MASK 0x00040000
#define METER_ECG_LDOFFP_DET_OFFSET 17
#define METER_ECG_LDOFFP_DET_MASK 0x00020000

//-----------------------------------
#define CFG_ANA_PMU_REG_CFG7_ADDR 0x1c
#define TSW_PD_ECG_OFFSET 31
#define TSW_PD_ECG_MASK 0x80000000
#define TSW_PD_PPG_OFFSET 30
#define TSW_PD_PPG_MASK 0x40000000
#define TSW_ECG_DET_OFFSET 26
#define TSW_ECG_DET_MASK 0x0C000000
#define TSW_ECG_FCHP_SEL_OFFSET 22
#define TSW_ECG_FCHP_SEL_MASK 0x01C00000
#define TSW_ECG_FCHP_BYPS_OFFSET 21
#define TSW_ECG_FCHP_BYPS_MASK 0x00200000
#define TSW_ECG_RLD_CTL_OFFSET 20
#define TSW_ECG_RLD_CTL_MASK 0x00100000

//-----------------------------------
#define CFG_ANA_PMU_REG_CFG8_ADDR 0x20
#define TSW_BIAS_PGA_CTL_OFFSET 28
#define TSW_BIAS_PGA_CTL_MASK 0x30000000
#define TSW_FCHP_BYPS_CH1_OFFSET 27
#define TSW_FCHP_BYPS_CH1_MASK 0x08000000
#define TSW_RC_CTL_OFFSET 23
#define TSW_RC_CTL_MASK 0x01800000
#define TSW_ATB_CTL_OFFSET 22
#define TSW_ATB_CTL_MASK 0x00400000
#define TSW_MTR2PAD_EN_OVR_OFFSET 18
#define TSW_MTR2PAD_EN_OVR_MASK 0x000C0000
#define TSW_MTR3PAD_EN_OVR_OFFSET 14
#define TSW_MTR3PAD_EN_OVR_MASK 0x0000C000
#define TSW_MTR2PAD_EN_NEG_OVR_OFFSET 10
#define TSW_MTR2PAD_EN_NEG_OVR_MASK 0x00000C00
#define TSW_TESTPAD_EN_OFFSET 9
#define TSW_TESTPAD_EN_MASK 0x00000200
#define TSW_IC2PAD_EN_OFFSET 8
#define TSW_IC2PAD_EN_MASK 0x00000100
#define TSW_BG2PAD_EN_OFFSET 7
#define TSW_BG2PAD_EN_MASK 0x00000080

//-----------------------------------
#define CFG_ANA_PMU_REG_CFG9_ADDR 0x24
#define LDO_DDR_PD_OFFSET 28
#define LDO_DDR_PD_MASK 0x30000000
#define LDO_DDR_LPWR_EN_OFFSET 24
#define LDO_DDR_LPWR_EN_MASK 0x03000000

//-----------------------------------
#define CFG_ANA_PMU_REG_CFG10_ADDR 0x28
#define ICCAL_OFFSET 24
#define ICCAL_MASK 0x1F000000
#define ICPTAT_CAL_EN_OFFSET 23
#define ICPTAT_CAL_EN_MASK 0x00800000
#define LP_BIASGEN_PD_OFFSET 22
#define LP_BIASGEN_PD_MASK 0x00400000
#define LPBG_CRRNT_SEL_OFFSET 21
#define LPBG_CRRNT_SEL_MASK 0x00200000

//-----------------------------------
#define CFG_ANA_PMU_REG_CFG11_ADDR 0x2c
#define PMU_LDO_CRRNT_SEL_OFFSET 28
#define PMU_LDO_CRRNT_SEL_MASK 0x70000000
#define PMU_LDO_VSEL_OFFSET 24
#define PMU_LDO_VSEL_MASK 0x0F000000
#define RCO_32K_CORE_ISEL_OFFSET 20
#define RCO_32K_CORE_ISEL_MASK 0x00F00000
#define RCO_32K_VREG_ISEL_OFFSET 16
#define RCO_32K_VREG_ISEL_MASK 0x000F0000
#define RCO_8M_PD_OFFSET 15
#define RCO_8M_PD_MASK 0x00008000
#define RCO_8M_RTBUF_EN_OFFSET 14
#define RCO_8M_RTBUF_EN_MASK 0x00004000
#define RCO_8M_DRV_OFFSET 10
#define RCO_8M_DRV_MASK 0x00000C00
#define ATB_AON_SEL_OFFSET 2
#define ATB_AON_SEL_MASK 0x0000007C

//-----------------------------------
#define CFG_ANA_PMU_REG_CFG12_ADDR 0x30
#define XTAL_32K_BIAS_SEL_OFFSET 28
#define XTAL_32K_BIAS_SEL_MASK 0x30000000
#define XTAL_32K_RTN_OFFSET 24
#define XTAL_32K_RTN_MASK 0x07000000
#define XTAL_32K_ISEL_OFFSET 20
#define XTAL_32K_ISEL_MASK 0x00700000
#define XTAL_32K_ICMP_SEL_OFFSET 16
#define XTAL_32K_ICMP_SEL_MASK 0x00070000
#define XTAL_32K_PD_OFFSET 15
#define XTAL_32K_PD_MASK 0x00008000

//-----------------------------------
#define CFG_ANA_PMU_REG_CFG13_ADDR 0x34
#define D_EN_PFM_DCDC_OFFSET 31
#define D_EN_PFM_DCDC_MASK 0x80000000
#define D_DIS_LMTCUR_DCDC_OFFSET 30
#define D_DIS_LMTCUR_DCDC_MASK 0x40000000
#define D_VREF_TUNE_DCDC_OFFSET 26
#define D_VREF_TUNE_DCDC_MASK 0x3C000000
#define D_FSW_DCDC_OFFSET 25
#define D_FSW_DCDC_MASK 0x02000000
#define D_REF_SEL_DCDC_OFFSET 24
#define D_REF_SEL_DCDC_MASK 0x01000000
#define D_EN_AUX_DCDC_OFFSET 23
#define D_EN_AUX_DCDC_MASK 0x00800000

//HW module read/write macro
#define ANA_PMU_WRAP_RF_READ_REG(addr) SOC_READ_REG(ANA_PMU_WRAP_RF_BASEADDR + addr)
#define ANA_PMU_WRAP_RF_WRITE_REG(addr,value) SOC_WRITE_REG(ANA_PMU_WRAP_RF_BASEADDR + addr,value)