//----------------------------------- #define CFG_UART_FIFO_ADDR 0x0 #define RXFIFO_RD_BYTE_OFFSET 0 #define RXFIFO_RD_BYTE_MASK 0x000000FF //----------------------------------- #define CFG_UART_INT_ENA_ADDR 0x4 #define BRK_DET_INT_ENA_OFFSET 18 #define BRK_DET_INT_ENA_MASK 0x00040000 #define CTS_CHG_INT_ENA_OFFSET 17 #define CTS_CHG_INT_ENA_MASK 0x00020000 #define DSR_CHG_INT_ENA_OFFSET 16 #define DSR_CHG_INT_ENA_MASK 0x00010000 #define RXFIFO_OVF_INT_ENA_OFFSET 15 #define RXFIFO_OVF_INT_ENA_MASK 0x00008000 #define FRM_ERR_INT_ENA_OFFSET 14 #define FRM_ERR_INT_ENA_MASK 0x00004000 #define PARITY_ERR_INT_ENA_OFFSET 13 #define PARITY_ERR_INT_ENA_MASK 0x00002000 #define TXFIFO_EMPTY_INT_ENA_OFFSET 12 #define TXFIFO_EMPTY_INT_ENA_MASK 0x00001000 #define RXFIFO_FULL_INT_ENA_OFFSET 11 #define RXFIFO_FULL_INT_ENA_MASK 0x00000800 #define CMD_AT_CHAR_DET_INT_ENA_OFFSET 10 #define CMD_AT_CHAR_DET_INT_ENA_MASK 0x00000400 #define TX_DONE_INT_ENA_OFFSET 9 #define TX_DONE_INT_ENA_MASK 0x00000200 #define TX_BRK_IDLE_DONE_INT_ENA_OFFSET 8 #define TX_BRK_IDLE_DONE_INT_ENA_MASK 0x00000100 #define TX_BRK_DONE_INT_ENA_OFFSET 7 #define TX_BRK_DONE_INT_ENA_MASK 0x00000080 #define GLITCH_DET_INT_ENA_OFFSET 6 #define GLITCH_DET_INT_ENA_MASK 0x00000040 #define SW_XOFF_INT_ENA_OFFSET 5 #define SW_XOFF_INT_ENA_MASK 0x00000020 #define SW_XON_INT_ENA_OFFSET 4 #define SW_XON_INT_ENA_MASK 0x00000010 #define RS485_CLASH_INT_ENA_OFFSET 3 #define RS485_CLASH_INT_ENA_MASK 0x00000008 #define RS485_FRM_ERR_INT_ENA_OFFSET 2 #define RS485_FRM_ERR_INT_ENA_MASK 0x00000004 #define RS485_PARITY_ERR_INT_ENA_OFFSET 1 #define RS485_PARITY_ERR_INT_ENA_MASK 0x00000002 #define RXFIFO_TOUT_INT_ENA_OFFSET 0 #define RXFIFO_TOUT_INT_ENA_MASK 0x00000001 //----------------------------------- #define CFG_UART_INT_CLR_ADDR 0x8 #define BRK_DET_INT_CLR_OFFSET 18 #define BRK_DET_INT_CLR_MASK 0x00040000 #define CTS_CHG_INT_CLR_OFFSET 17 #define CTS_CHG_INT_CLR_MASK 0x00020000 #define DSR_CHG_INT_CLR_OFFSET 16 #define DSR_CHG_INT_CLR_MASK 0x00010000 #define RXFIFO_OVF_INT_CLR_OFFSET 15 #define RXFIFO_OVF_INT_CLR_MASK 0x00008000 #define FRM_ERR_INT_CLR_OFFSET 14 #define FRM_ERR_INT_CLR_MASK 0x00004000 #define PARITY_ERR_INT_CLR_OFFSET 13 #define PARITY_ERR_INT_CLR_MASK 0x00002000 #define TXFIFO_EMPTY_INT_CLR_OFFSET 12 #define TXFIFO_EMPTY_INT_CLR_MASK 0x00001000 #define RXFIFO_FULL_INT_CLR_OFFSET 11 #define RXFIFO_FULL_INT_CLR_MASK 0x00000800 #define CMD_AT_CHAR_DET_INT_CLR_OFFSET 10 #define CMD_AT_CHAR_DET_INT_CLR_MASK 0x00000400 #define TX_DONE_INT_CLR_OFFSET 9 #define TX_DONE_INT_CLR_MASK 0x00000200 #define TX_BRK_IDLE_DONE_INT_CLR_OFFSET 8 #define TX_BRK_IDLE_DONE_INT_CLR_MASK 0x00000100 #define TX_BRK_DONE_INT_CLR_OFFSET 7 #define TX_BRK_DONE_INT_CLR_MASK 0x00000080 #define GLITCH_DET_INT_CLR_OFFSET 6 #define GLITCH_DET_INT_CLR_MASK 0x00000040 #define SW_XOFF_INT_CLR_OFFSET 5 #define SW_XOFF_INT_CLR_MASK 0x00000020 #define SW_XON_INT_CLR_OFFSET 4 #define SW_XON_INT_CLR_MASK 0x00000010 #define RS485_CLASH_INT_CLR_OFFSET 3 #define RS485_CLASH_INT_CLR_MASK 0x00000008 #define RS485_FRM_ERR_INT_CLR_OFFSET 2 #define RS485_FRM_ERR_INT_CLR_MASK 0x00000004 #define RS485_PARITY_ERR_INT_CLR_OFFSET 1 #define RS485_PARITY_ERR_INT_CLR_MASK 0x00000002 #define RXFIFO_TOUT_INT_CLR_OFFSET 0 #define RXFIFO_TOUT_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_UART_INT_RAW_ADDR 0xc #define BRK_DET_INT_RAW_OFFSET 18 #define BRK_DET_INT_RAW_MASK 0x00040000 #define CTS_CHG_INT_RAW_OFFSET 17 #define CTS_CHG_INT_RAW_MASK 0x00020000 #define DSR_CHG_INT_RAW_OFFSET 16 #define DSR_CHG_INT_RAW_MASK 0x00010000 #define RXFIFO_OVF_INT_RAW_OFFSET 15 #define RXFIFO_OVF_INT_RAW_MASK 0x00008000 #define FRM_ERR_INT_RAW_OFFSET 14 #define FRM_ERR_INT_RAW_MASK 0x00004000 #define PARITY_ERR_INT_RAW_OFFSET 13 #define PARITY_ERR_INT_RAW_MASK 0x00002000 #define TXFIFO_EMPTY_INT_RAW_OFFSET 12 #define TXFIFO_EMPTY_INT_RAW_MASK 0x00001000 #define RXFIFO_FULL_INT_RAW_OFFSET 11 #define RXFIFO_FULL_INT_RAW_MASK 0x00000800 #define CMD_AT_CHAR_DET_INT_RAW_OFFSET 10 #define CMD_AT_CHAR_DET_INT_RAW_MASK 0x00000400 #define TX_DONE_INT_RAW_OFFSET 9 #define TX_DONE_INT_RAW_MASK 0x00000200 #define TX_BRK_IDLE_DONE_INT_RAW_OFFSET 8 #define TX_BRK_IDLE_DONE_INT_RAW_MASK 0x00000100 #define TX_BRK_DONE_INT_RAW_OFFSET 7 #define TX_BRK_DONE_INT_RAW_MASK 0x00000080 #define GLITCH_DET_INT_RAW_OFFSET 6 #define GLITCH_DET_INT_RAW_MASK 0x00000040 #define SW_XOFF_INT_RAW_OFFSET 5 #define SW_XOFF_INT_RAW_MASK 0x00000020 #define SW_XON_INT_RAW_OFFSET 4 #define SW_XON_INT_RAW_MASK 0x00000010 #define RS485_CLASH_INT_RAW_OFFSET 3 #define RS485_CLASH_INT_RAW_MASK 0x00000008 #define RS485_FRM_ERR_INT_RAW_OFFSET 2 #define RS485_FRM_ERR_INT_RAW_MASK 0x00000004 #define RS485_PARITY_ERR_INT_RAW_OFFSET 1 #define RS485_PARITY_ERR_INT_RAW_MASK 0x00000002 #define RXFIFO_TOUT_INT_RAW_OFFSET 0 #define RXFIFO_TOUT_INT_RAW_MASK 0x00000001 //----------------------------------- #define CFG_UART_INT_ST_ADDR 0x10 #define BRK_DET_INT_ST_OFFSET 18 #define BRK_DET_INT_ST_MASK 0x00040000 #define CTS_CHG_INT_ST_OFFSET 17 #define CTS_CHG_INT_ST_MASK 0x00020000 #define DSR_CHG_INT_ST_OFFSET 16 #define DSR_CHG_INT_ST_MASK 0x00010000 #define RXFIFO_OVF_INT_ST_OFFSET 15 #define RXFIFO_OVF_INT_ST_MASK 0x00008000 #define FRM_ERR_INT_ST_OFFSET 14 #define FRM_ERR_INT_ST_MASK 0x00004000 #define PARITY_ERR_INT_ST_OFFSET 13 #define PARITY_ERR_INT_ST_MASK 0x00002000 #define TXFIFO_EMPTY_INT_ST_OFFSET 12 #define TXFIFO_EMPTY_INT_ST_MASK 0x00001000 #define RXFIFO_FULL_INT_ST_OFFSET 11 #define RXFIFO_FULL_INT_ST_MASK 0x00000800 #define CMD_AT_CHAR_DET_INT_ST_OFFSET 10 #define CMD_AT_CHAR_DET_INT_ST_MASK 0x00000400 #define TX_DONE_INT_ST_OFFSET 9 #define TX_DONE_INT_ST_MASK 0x00000200 #define TX_BRK_IDLE_DONE_INT_ST_OFFSET 8 #define TX_BRK_IDLE_DONE_INT_ST_MASK 0x00000100 #define TX_BRK_DONE_INT_ST_OFFSET 7 #define TX_BRK_DONE_INT_ST_MASK 0x00000080 #define GLITCH_DET_INT_ST_OFFSET 6 #define GLITCH_DET_INT_ST_MASK 0x00000040 #define SW_XOFF_INT_ST_OFFSET 5 #define SW_XOFF_INT_ST_MASK 0x00000020 #define SW_XON_INT_ST_OFFSET 4 #define SW_XON_INT_ST_MASK 0x00000010 #define RS485_CLASH_INT_ST_OFFSET 3 #define RS485_CLASH_INT_ST_MASK 0x00000008 #define RS485_FRM_ERR_INT_ST_OFFSET 2 #define RS485_FRM_ERR_INT_ST_MASK 0x00000004 #define RS485_PARITY_ERR_INT_ST_OFFSET 1 #define RS485_PARITY_ERR_INT_ST_MASK 0x00000002 #define RXFIFO_TOUT_INT_ST_OFFSET 0 #define RXFIFO_TOUT_INT_ST_MASK 0x00000001 //----------------------------------- #define CFG_UART_CTRL0_ADDR 0x14 #define FORCE_TXD_BRK_OFFSET 30 #define FORCE_TXD_BRK_MASK 0x40000000 #define TX_FLOW_EN_OFFSET 29 #define TX_FLOW_EN_MASK 0x20000000 #define UART_LOOPBACK_OFFSET 28 #define UART_LOOPBACK_MASK 0x10000000 #define IRDA_RX_INV_OFFSET 27 #define IRDA_RX_INV_MASK 0x08000000 #define IRDA_TX_INV_OFFSET 26 #define IRDA_TX_INV_MASK 0x04000000 #define IRDA_WCTL_OFFSET 25 #define IRDA_WCTL_MASK 0x02000000 #define IRDA_TX_EN_OFFSET 24 #define IRDA_TX_EN_MASK 0x01000000 #define IRDA_DPLX_OFFSET 23 #define IRDA_DPLX_MASK 0x00800000 #define TXD_BRK_OFFSET 22 #define TXD_BRK_MASK 0x00400000 #define SW_DTR_OFFSET 21 #define SW_DTR_MASK 0x00200000 #define SW_RTS_OFFSET 20 #define SW_RTS_MASK 0x00100000 #define STOP_BIT_NUM_OFFSET 18 #define STOP_BIT_NUM_MASK 0x000C0000 #define BIT_NUM_OFFSET 16 #define BIT_NUM_MASK 0x00030000 #define PARITY_EN_OFFSET 15 #define PARITY_EN_MASK 0x00008000 #define PARITY_OFFSET 14 #define PARITY_MASK 0x00004000 #define UART_TICK_REF_ALWAYS_ON_OFFSET 13 #define UART_TICK_REF_ALWAYS_ON_MASK 0x00002000 #define UART_ERR_WR_MASK_OFFSET 12 #define UART_ERR_WR_MASK_MASK 0x00001000 #define UART_REG_CLK_EN_OFFSET 11 #define UART_REG_CLK_EN_MASK 0x00000800 #define UART_DTR_INV_OFFSET 10 #define UART_DTR_INV_MASK 0x00000400 #define UART_RTS_INV_OFFSET 9 #define UART_RTS_INV_MASK 0x00000200 #define UART_TXD_INV_OFFSET 8 #define UART_TXD_INV_MASK 0x00000100 #define UART_DSR_INV_OFFSET 7 #define UART_DSR_INV_MASK 0x00000080 #define UART_CTS_INV_OFFSET 6 #define UART_CTS_INV_MASK 0x00000040 #define UART_RXD_INV_OFFSET 3 #define UART_RXD_INV_MASK 0x00000008 #define TXFIFO_RST_OFFSET 2 #define TXFIFO_RST_MASK 0x00000004 #define RXFIFO_RST_OFFSET 1 #define RXFIFO_RST_MASK 0x00000002 #define IRDA_EN_OFFSET 0 #define IRDA_EN_MASK 0x00000001 //----------------------------------- #define CFG_UART_CTRL1_ADDR 0x18 #define RX_TOUT_EN_OFFSET 31 #define RX_TOUT_EN_MASK 0x80000000 #define RX_TOUT_THRHD_OFFSET 24 #define RX_TOUT_THRHD_MASK 0x7F000000 #define RX_FLOW_EN_OFFSET 23 #define RX_FLOW_EN_MASK 0x00800000 #define RX_FLOW_THRHD_OFFSET 16 #define RX_FLOW_THRHD_MASK 0x007F0000 #define TXFIFO_EMPTY_THRHD_OFFSET 8 #define TXFIFO_EMPTY_THRHD_MASK 0x00007F00 #define RXFIFO_FULL_THRHD_OFFSET 0 #define RXFIFO_FULL_THRHD_MASK 0x0000007F //----------------------------------- #define CFG_UART_CLK_CFG_ADDR 0x1c #define UART_CLKDIV_FRAG_OFFSET 20 #define UART_CLKDIV_FRAG_MASK 0x00F00000 #define UART_CLKDIV_OFFSET 0 #define UART_CLKDIV_MASK 0x000FFFFF //----------------------------------- #define CFG_UART_BAUD_CFG_ADDR 0x20 #define GLITCH_FILT_OFFSET 8 #define GLITCH_FILT_MASK 0x0000FF00 #define AUTOBAUD_EN_OFFSET 0 #define AUTOBAUD_EN_MASK 0x00000001 //----------------------------------- #define CFG_UART_STS_ADDR 0x24 #define TXD_OFFSET 31 #define TXD_MASK 0x80000000 #define RTSN_OFFSET 30 #define RTSN_MASK 0x40000000 #define DTRN_OFFSET 29 #define DTRN_MASK 0x20000000 #define ST_UTX_OUT_OFFSET 24 #define ST_UTX_OUT_MASK 0x0F000000 #define TXFIFO_CNT_OFFSET 16 #define TXFIFO_CNT_MASK 0x00FF0000 #define RXD_OFFSET 14 #define RXD_MASK 0x00004000 #define CTSN_OFFSET 13 #define CTSN_MASK 0x00002000 #define DSRN_OFFSET 12 #define DSRN_MASK 0x00001000 #define ST_URX_OUT_OFFSET 8 #define ST_URX_OUT_MASK 0x00000F00 #define RXFIFO_CNT_OFFSET 0 #define RXFIFO_CNT_MASK 0x000000FF //----------------------------------- #define CFG_UART_RAM_TX_STS_ADDR 0x28 #define MEM_TX_STATUS_OFFSET 0 #define MEM_TX_STATUS_MASK 0x00FFFFFF //----------------------------------- #define CFG_UART_RAM_RX_STS_ADDR 0x2c #define MEM_RX_STATUS_OFFSET 0 #define MEM_RX_STATUS_MASK 0x00FFFFFF //----------------------------------- #define CFG_UART_RAM_CNT_STS_ADDR 0x30 #define TX_MEM_CNT_OFFSET 3 #define TX_MEM_CNT_MASK 0x00000038 #define RX_MEM_CNT_OFFSET 0 #define RX_MEM_CNT_MASK 0x00000007 //----------------------------------- #define CFG_UART_LOW_PULSE_ADDR 0x34 #define LOWPULSE_MIN_CNT_OFFSET 0 #define LOWPULSE_MIN_CNT_MASK 0x000FFFFF //----------------------------------- #define CFG_UART_HIG_HPULSE_ADDR 0x38 #define HIGHPULSE_MIN_CNT_OFFSET 0 #define HIGHPULSE_MIN_CNT_MASK 0x000FFFFF //----------------------------------- #define CFG_UART_RXD_COUNT_ADDR 0x3c #define RXD_EDGE_CNT_OFFSET 0 #define RXD_EDGE_CNT_MASK 0x000003FF //----------------------------------- #define CFG_UART_FLOW_CFG_ADDR 0x40 #define UART_FORCE_XOFF_OFFSET 5 #define UART_FORCE_XOFF_MASK 0x00000020 #define UART_FORCE_XON_OFFSET 4 #define UART_FORCE_XON_MASK 0x00000010 #define UART_SEND_XOFF_OFFSET 3 #define UART_SEND_XOFF_MASK 0x00000008 #define UART_SEND_XON_OFFSET 2 #define UART_SEND_XON_MASK 0x00000004 #define UART_XONOFF_DEL_OFFSET 1 #define UART_XONOFF_DEL_MASK 0x00000002 #define UART_SW_FLOW_CON_EN_OFFSET 0 #define UART_SW_FLOW_CON_EN_MASK 0x00000001 //----------------------------------- #define CFG_UART_SLEEP_CFG_ADDR 0x44 #define UART_ACTIVE_THRESHOLD_OFFSET 0 #define UART_ACTIVE_THRESHOLD_MASK 0x000003FF //----------------------------------- #define CFG_UART_SWFC_CFG_ADDR 0x48 #define UART_XOFF_CHAR_OFFSET 24 #define UART_XOFF_CHAR_MASK 0xFF000000 #define UART_XON_CHAR_OFFSET 16 #define UART_XON_CHAR_MASK 0x00FF0000 #define UART_XOFF_THRESHOLD_OFFSET 8 #define UART_XOFF_THRESHOLD_MASK 0x0000FF00 #define UART_XON_THRESHOLD_OFFSET 0 #define UART_XON_THRESHOLD_MASK 0x000000FF //----------------------------------- #define CFG_UART_IDLE_CFG_ADDR 0x4c #define UART_TX_BRK_NUM_OFFSET 20 #define UART_TX_BRK_NUM_MASK 0x0FF00000 #define UART_TX_IDLE_NUM_OFFSET 10 #define UART_TX_IDLE_NUM_MASK 0x000FFC00 #define RX_IDLE_THRHD_OFFSET 0 #define RX_IDLE_THRHD_MASK 0x000003FF //----------------------------------- #define CFG_UART_RS485_CFG_ADDR 0x50 #define RS485_TX_DLY_NUM_OFFSET 6 #define RS485_TX_DLY_NUM_MASK 0x000003C0 #define RS485_RX_DLY_NUM_OFFSET 5 #define RS485_RX_DLY_NUM_MASK 0x00000020 #define RS485RXBY_TX_EN_OFFSET 4 #define RS485RXBY_TX_EN_MASK 0x00000010 #define RS485TX_RX_EN_OFFSET 3 #define RS485TX_RX_EN_MASK 0x00000008 #define DL1_EN_OFFSET 2 #define DL1_EN_MASK 0x00000004 #define DL0_EN_OFFSET 1 #define DL0_EN_MASK 0x00000002 #define RS485_EN_OFFSET 0 #define RS485_EN_MASK 0x00000001 //----------------------------------- #define CFG_UART_ATCMD_PRE_CNT_ADDR 0x54 #define PRE_IDLE_NUM_OFFSET 0 #define PRE_IDLE_NUM_MASK 0x00FFFFFF //----------------------------------- #define CFG_UART_ATCMD_POST_CNT_ADDR 0x58 #define POST_IDLE_NUM_OFFSET 0 #define POST_IDLE_NUM_MASK 0x00FFFFFF //----------------------------------- #define CFG_UART_ATCMD_GAP_TOUT_ADDR 0x5c #define RX_GAP_TOUT_OFFSET 0 #define RX_GAP_TOUT_MASK 0x00FFFFFF //----------------------------------- #define CFG_UART_ATCMD_CHAR_ADDR 0x60 #define CHAR_NUM_OFFSET 8 #define CHAR_NUM_MASK 0x0000FF00 #define AT_CMD_CHAR_OFFSET 0 #define AT_CMD_CHAR_MASK 0x000000FF //----------------------------------- #define CFG_UART_RAM_CFG_ADDR 0x64 #define TX_MEM_EMPTY_THRHD_OFFSET 28 #define TX_MEM_EMPTY_THRHD_MASK 0x70000000 #define RX_MEM_FULL_THRHD_OFFSET 25 #define RX_MEM_FULL_THRHD_MASK 0x0E000000 #define UART_XOFF_THRESHOLD_H2_OFFSET 23 #define UART_XOFF_THRESHOLD_H2_MASK 0x01800000 #define UART_XON_THRESHOLD_H2_OFFSET 21 #define UART_XON_THRESHOLD_H2_MASK 0x00600000 #define RX_TOUT_THRHD_H3_OFFSET 18 #define RX_TOUT_THRHD_H3_MASK 0x001C0000 #define RX_FLOW_THRHD_H3_OFFSET 15 #define RX_FLOW_THRHD_H3_MASK 0x00038000 #define REG_TX_SIZE_OFFSET 8 #define REG_TX_SIZE_MASK 0x00000F00 #define REG_RX_SIZE_OFFSET 4 #define REG_RX_SIZE_MASK 0x000000F0 #define REG_MEM_PD_OFFSET 0 #define REG_MEM_PD_MASK 0x00000001 //HW module read/write macro #define APB_UART_READ_REG(addr) SOC_READ_REG(APB_UART0_BASEADDR + addr) #define APB_UART_WRITE_REG(addr,value) SOC_WRITE_REG(APB_UART0_BASEADDR + addr,value) #define APB_UART1_READ_REG(addr) SOC_READ_REG(APB_UART1_BASEADDR + addr) #define APB_UART1_WRITE_REG(addr,value) SOC_WRITE_REG(APB_UART1_BASEADDR + addr,value) #define APB_UART2_READ_REG(addr) SOC_READ_REG(APB_UART2_BASEADDR + addr) #define APB_UART2_WRITE_REG(addr,value) SOC_WRITE_REG(APB_UART2_BASEADDR + addr,value) #define APB_UART3_READ_REG(addr) SOC_READ_REG(APB_UART3_BASEADDR + addr) #define APB_UART3_WRITE_REG(addr,value) SOC_WRITE_REG(APB_UART3_BASEADDR + addr,value)