//-----------------------------------
#define CFG_EFUSE_INFO_ADDR 0x0000
#define APB_RF_VER_OFFSET 0
#define APB_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_EFUSE_CMD_ADDR 0x0004
#define REG_IDLE_OFFSET 24
#define REG_IDLE_MASK 0x01000000
#define REG_PGM_OFFSET 16
#define REG_PGM_MASK 0x00FF0000
#define REG_A_OFFSET 0
#define REG_A_MASK 0x000007FF

//-----------------------------------
#define CFG_EFUSE_ERR_CNT_ADDR 0x0008
#define ERROR_BIT_CNT_OFFSET 0
#define ERROR_BIT_CNT_MASK 0x00000FFF

//-----------------------------------
#define CFG_EFUSE_REG_0_ADDR 0x0100
#define EFUSE_0_OFFSET 0
#define EFUSE_0_MASK 0xFFFFFFFF

#if 0
//-----------------------------------
#define CFG_EFUSE_BITS32_1_ADDR 0x0104
#define EFUSE_1_OFFSET 0
#define EFUSE_1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_2_ADDR 0x0108
#define EFUSE_2_OFFSET 0
#define EFUSE_2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_3_ADDR 0x010C
#define EFUSE_3_OFFSET 0
#define EFUSE_3_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_4_ADDR 0x0110
#define EFUSE_4_OFFSET 0
#define EFUSE_4_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_5_ADDR 0x0114
#define EFUSE_5_OFFSET 0
#define EFUSE_5_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_6_ADDR 0x0118
#define EFUSE_6_OFFSET 0
#define EFUSE_6_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_BITS32_7_ADDR 0x011C
#define EFUSE_7_OFFSET 0
#define EFUSE_7_MASK 0xFFFFFFFF
#endif

//HW module read/write macro
#define EFUSE_DIG_READ_REG(addr) SOC_READ_REG(EFUSE_DIG_BASEADDR + addr)
#define EFUSE_DIG_WRITE_REG(addr,value) SOC_WRITE_REG(EFUSE_DIG_BASEADDR + addr,value)