//-----------------------------------
#define CFG_EPARSER_REG_RVER_ADDR 0x0
#define EPARSER_RF_VER_OFFSET 0
#define EPARSER_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_EPARSER_DMA_CFG_ADDR 0x4
#define OUT_BIT_ORDER_SEL_OFFSET 7
#define OUT_BIT_ORDER_SEL_MASK 0x00000080
#define OUT_BYTE_ORDER_SEL_OFFSET 6
#define OUT_BYTE_ORDER_SEL_MASK 0x00000040
#define IN_BIT_ORDER_SEL_OFFSET 5
#define IN_BIT_ORDER_SEL_MASK 0x00000020
#define IN_BYTE_ORDER_SEL_OFFSET 4
#define IN_BYTE_ORDER_SEL_MASK 0x00000010
#define DMA_STOP_OFFSET 2
#define DMA_STOP_MASK 0x00000004
#define DMA_RESTART_OFFSET 1
#define DMA_RESTART_MASK 0x00000002
#define DMA_START_OFFSET 0
#define DMA_START_MASK 0x00000001

//-----------------------------------
#define CFG_DMA_LINK_ADDR_CFG_ADDR 0x8
#define DMA_LINK_ADDR_OFFSET 0
#define DMA_LINK_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_INT_RAW_ADDR 0x10
#define EDMA_ALL_DECR_INT_RAW_OFFSET 1
#define EDMA_ALL_DECR_INT_RAW_MASK 0x00000002
#define EDMA_CURR_DECR_INT_RAW_OFFSET 0
#define EDMA_CURR_DECR_INT_RAW_MASK 0x00000001

//-----------------------------------
#define CFG_DMA_INT_ST_ADDR 0x14
#define EDMA_ALL_DECR_INT_ST_OFFSET 1
#define EDMA_ALL_DECR_INT_ST_MASK 0x00000002
#define EDMA_CURR_DECR_INT_ST_OFFSET 0
#define EDMA_CURR_DECR_INT_ST_MASK 0x00000001

//-----------------------------------
#define CFG_DMA_INT_ENA_ADDR 0x18
#define EDMA_ALL_DECR_INT_ENA_OFFSET 1
#define EDMA_ALL_DECR_INT_ENA_MASK 0x00000002
#define EDMA_CURR_DECR_INT_ENA_OFFSET 0
#define EDMA_CURR_DECR_INT_ENA_MASK 0x00000001

//-----------------------------------
#define CFG_DMA_INT_CLR_ADDR 0x1C
#define EDMA_ALL_DECR_INT_CLR_OFFSET 1
#define EDMA_ALL_DECR_INT_CLR_MASK 0x00000002
#define EDMA_CURR_DECR_INT_CLR_OFFSET 0
#define EDMA_CURR_DECR_INT_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_DMA_RESET_ADDR_CFG_ADDR 0x20
#define EDMA_RESET_DECR_ADDR_OFFSET 0
#define EDMA_RESET_DECR_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_DBG_BUS_ADDR 0x24
#define DMA_SIG_DBG_BUS_OFFSET 0
#define DMA_SIG_DBG_BUS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PARSER_ACTION_ADDR 0x28
#define REG_HEAD_LEN_VLD_OFFSET 25
#define REG_HEAD_LEN_VLD_MASK 0x02000000
#define REG_HEAD_LEN_OFFSET 18
#define REG_HEAD_LEN_MASK 0x01FC0000
#define REG_ACL_HIT_L2_OFFSET 17
#define REG_ACL_HIT_L2_MASK 0x00020000
#define REG_ACL_ACTION_L2_OFFSET 12
#define REG_ACL_ACTION_L2_MASK 0x0001F000
#define REG_ACL_HIT_L3_OFFSET 11
#define REG_ACL_HIT_L3_MASK 0x00000800
#define REG_ACL_ACTION_L3_OFFSET 6
#define REG_ACL_ACTION_L3_MASK 0x000007C0
#define REG_ACL_HIT_LU_OFFSET 5
#define REG_ACL_HIT_LU_MASK 0x00000020
#define REG_ACL_ACTION_LU_OFFSET 0
#define REG_ACL_ACTION_LU_MASK 0x0000001F

//HW module read/write macro
#define EPARSER_READ_REG(addr) SOC_READ_REG(EPARSER_BASEADDR + addr)
#define EPARSER_WRITE_REG(addr,value) SOC_WRITE_REG(EPARSER_BASEADDR + addr,value)