//-----------------------------------
#define CFG_GTMR_RVER_ADDR 0x0000
#define GTMR_RF_VER_OFFSET 0
#define GTMR_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_GTMR0_CTRL_CFG_ADDR 0x0004
#define TMR0_TICK_SEL_OFFSET 4
#define TMR0_TICK_SEL_MASK 0x00000010
#define TMR0_PAUSE_CFG_OFFSET 3
#define TMR0_PAUSE_CFG_MASK 0x00000008
#define TMR0_INT_ENA_OFFSET 2
#define TMR0_INT_ENA_MASK 0x00000004
#define TMR0_ENA_CFG_OFFSET 1
#define TMR0_ENA_CFG_MASK 0x00000002
#define TMR0_MODE_CFG_OFFSET 0
#define TMR0_MODE_CFG_MASK 0x00000001

//-----------------------------------
#define CFG_GTMR0_CFG_ADDR 0x0008
#define TMR0_CFG_OFFSET 0
#define TMR0_CFG_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GTMR0_INT_STATUS_ADDR 0x000C
#define TMR0_INT_RAW_OFFSET 1
#define TMR0_INT_RAW_MASK 0x00000002
#define TMR0_INT_STS_OFFSET 0
#define TMR0_INT_STS_MASK 0x00000001

//-----------------------------------
#define CFG_GTMR0_VAL_ADDR 0x0010
#define TMR0_CNT_OFFSET 0
#define TMR0_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GTMR0_CLR_ADDR 0x0014
#define TMR0_INT_CLR_OFFSET 1
#define TMR0_INT_CLR_MASK 0x00000002
#define TMR0_CNT_CLR_OFFSET 0
#define TMR0_CNT_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_GTMR1_CTRL_CFG_ADDR 0x0018
#define TMR1_TICK_SEL_OFFSET 4
#define TMR1_TICK_SEL_MASK 0x00000010
#define TMR1_PAUSE_CFG_OFFSET 3
#define TMR1_PAUSE_CFG_MASK 0x00000008
#define TMR1_INT_ENA_OFFSET 2
#define TMR1_INT_ENA_MASK 0x00000004
#define TMR1_ENA_CFG_OFFSET 1
#define TMR1_ENA_CFG_MASK 0x00000002
#define TMR1_MODE_CFG_OFFSET 0
#define TMR1_MODE_CFG_MASK 0x00000001

//-----------------------------------
#define CFG_GTMR1_CFG_ADDR 0x001C
#define TMR1_CFG_OFFSET 0
#define TMR1_CFG_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GTMR1_INT_STATUS_ADDR 0x0020
#define TMR1_INT_RAW_OFFSET 1
#define TMR1_INT_RAW_MASK 0x00000002
#define TMR1_INT_STS_OFFSET 0
#define TMR1_INT_STS_MASK 0x00000001

//-----------------------------------
#define CFG_GTMR1_VAL_ADDR 0x0024
#define TMR1_CNT_OFFSET 0
#define TMR1_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GTMR1_CLR_ADDR 0x0028
#define TMR1_INT_CLR_OFFSET 1
#define TMR1_INT_CLR_MASK 0x00000002
#define TMR1_CNT_CLR_OFFSET 0
#define TMR1_CNT_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_GTMR2_CTRL_CFG_ADDR 0x002C
#define TMR2_TICK_SEL_OFFSET 4
#define TMR2_TICK_SEL_MASK 0x00000010
#define TMR2_PAUSE_CFG_OFFSET 3
#define TMR2_PAUSE_CFG_MASK 0x00000008
#define TMR2_INT_ENA_OFFSET 2
#define TMR2_INT_ENA_MASK 0x00000004
#define TMR2_ENA_CFG_OFFSET 1
#define TMR2_ENA_CFG_MASK 0x00000002
#define TMR2_MODE_CFG_OFFSET 0
#define TMR2_MODE_CFG_MASK 0x00000001

//-----------------------------------
#define CFG_GTMR2_CFG_ADDR 0x0030
#define TMR2_CFG_OFFSET 0
#define TMR2_CFG_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GTMR2_INT_STATUS_ADDR 0x0034
#define TMR2_INT_RAW_OFFSET 1
#define TMR2_INT_RAW_MASK 0x00000002
#define TMR2_INT_STS_OFFSET 0
#define TMR2_INT_STS_MASK 0x00000001

//-----------------------------------
#define CFG_GTMR2_VAL_ADDR 0x0038
#define TMR2_CNT_OFFSET 0
#define TMR2_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GTMR2_CLR_ADDR 0x003C
#define TMR2_INT_CLR_OFFSET 1
#define TMR2_INT_CLR_MASK 0x00000002
#define TMR2_CNT_CLR_OFFSET 0
#define TMR2_CNT_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_GTMR3_CTRL_CFG_ADDR 0x0040
#define TMR3_TICK_SEL_OFFSET 4
#define TMR3_TICK_SEL_MASK 0x00000010
#define TMR3_PAUSE_CFG_OFFSET 3
#define TMR3_PAUSE_CFG_MASK 0x00000008
#define TMR3_INT_ENA_OFFSET 2
#define TMR3_INT_ENA_MASK 0x00000004
#define TMR3_ENA_CFG_OFFSET 1
#define TMR3_ENA_CFG_MASK 0x00000002
#define TMR3_MODE_CFG_OFFSET 0
#define TMR3_MODE_CFG_MASK 0x00000001

//-----------------------------------
#define CFG_GTMR3_CFG_ADDR 0x0044
#define TMR3_CFG_OFFSET 0
#define TMR3_CFG_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GTMR3_INT_STATUS_ADDR 0x0048
#define TMR3_INT_RAW_OFFSET 1
#define TMR3_INT_RAW_MASK 0x00000002
#define TMR3_INT_STS_OFFSET 0
#define TMR3_INT_STS_MASK 0x00000001

//-----------------------------------
#define CFG_GTMR3_VAL_ADDR 0x004C
#define TMR3_CNT_OFFSET 0
#define TMR3_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GTMR3_CLR_ADDR 0x0050
#define TMR3_INT_CLR_OFFSET 1
#define TMR3_INT_CLR_MASK 0x00000002
#define TMR3_CNT_CLR_OFFSET 0
#define TMR3_CNT_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_GTMR0_DIV_ADDR 0x0054
#define TMR0_DIV_OFFSET 0
#define TMR0_DIV_MASK 0x000000FF

//-----------------------------------
#define CFG_GTMR1_DIV_ADDR 0x0058
#define TMR1_DIV_OFFSET 0
#define TMR1_DIV_MASK 0x000000FF

//-----------------------------------
#define CFG_GTMR2_DIV_ADDR 0x005C
#define TMR2_DIV_OFFSET 0
#define TMR2_DIV_MASK 0x000000FF

//-----------------------------------
#define CFG_GTMR3_DIV_ADDR 0x0060
#define TMR3_DIV_OFFSET 0
#define TMR3_DIV_MASK 0x000000FF

//HW module read/write macro
#define GTMR0_READ_REG(addr) SOC_READ_REG(GTMR0_BASEADDR + addr)
#define GTMR0_WRITE_REG(addr,value) SOC_WRITE_REG(GTMR0_BASEADDR + addr,value)
#define GTMR1_READ_REG(addr) SOC_READ_REG(GTMR1_BASEADDR + addr)
#define GTMR1_WRITE_REG(addr,value) SOC_WRITE_REG(GTMR1_BASEADDR + addr,value)
#define GTMR2_READ_REG(addr) SOC_READ_REG(GTMR2_BASEADDR + addr)
#define GTMR2_WRITE_REG(addr,value) SOC_WRITE_REG(GTMR2_BASEADDR + addr,value)