//----------------------------------- #define CFG_LEDC0_CONF_ADDR 0x0040 #define LEDC0_SIGOUT_SEL_OFFSET 4 #define LEDC0_SIGOUT_SEL_MASK 0x00000010 #define LEDC0_SIGOUT_IDLE_VALUE_OFFSET 3 #define LEDC0_SIGOUT_IDLE_VALUE_MASK 0x00000008 #define LEDC0_SIGOUT_EB_OFFSET 2 #define LEDC0_SIGOUT_EB_MASK 0x00000004 #define LEDC0_TIMER_SEL_OFFSET 0 #define LEDC0_TIMER_SEL_MASK 0x00000003 //----------------------------------- #define CFG_LEDC0_L2H_VALUE_ADDR 0x0044 #define LEDC0_L2H_VALUE_OFFSET 0 #define LEDC0_L2H_VALUE_MASK 0x000FFFFF //----------------------------------- #define CFG_LEDC0_TARGET_VALUE_ADDR 0x0048 #define LEDC0_TARGET_VALUE_OFFSET 0 #define LEDC0_TARGET_VALUE_MASK 0x01FFFFFF //----------------------------------- #define CFG_LEDC0_TARGET_CONF_ADDR 0x004C #define LEDC0_TARGET_SHADOW_EN_OFFSET 31 #define LEDC0_TARGET_SHADOW_EN_MASK 0x80000000 #define LEDC0_TARGET_INC_OR_DEC_OFFSET 30 #define LEDC0_TARGET_INC_OR_DEC_MASK 0x40000000 #define LEDC0_TARGET_INC_OR_DEC_NUM_OFFSET 20 #define LEDC0_TARGET_INC_OR_DEC_NUM_MASK 0x3FF00000 #define LEDC0_TARGET_INC_OR_DEC_CYCLE_OFFSET 10 #define LEDC0_TARGET_INC_OR_DEC_CYCLE_MASK 0x000FFC00 #define LEDC0_TARGET_INC_OR_DEC_SCOPE_OFFSET 0 #define LEDC0_TARGET_INC_OR_DEC_SCOPE_MASK 0x000003FF //----------------------------------- #define CFG_LEDC0_READ_TARGET_VALUE_ADDR 0x0050 #define LEDC0_READ_TARGET_OFFSET 0 #define LEDC0_READ_TARGET_MASK 0x01FFFFFF //----------------------------------- #define CFG_LEDC1_CONF_ADDR 0x0054 #define LEDC1_SIGOUT_SEL_OFFSET 4 #define LEDC1_SIGOUT_SEL_MASK 0x00000010 #define LEDC1_SIGOUT_IDLE_VALUE_OFFSET 3 #define LEDC1_SIGOUT_IDLE_VALUE_MASK 0x00000008 #define LEDC1_SIGOUT_EB_OFFSET 2 #define LEDC1_SIGOUT_EB_MASK 0x00000004 #define LEDC1_TIMER_SEL_OFFSET 0 #define LEDC1_TIMER_SEL_MASK 0x00000003 //----------------------------------- #define CFG_LEDC1_L2H_VALUE_ADDR 0x0058 #define LEDC1_L2H_VALUE_OFFSET 0 #define LEDC1_L2H_VALUE_MASK 0x000FFFFF //----------------------------------- #define CFG_LEDC1_TARGET_VALUE_ADDR 0x005C #define LEDC1_TARGET_VALUE_OFFSET 0 #define LEDC1_TARGET_VALUE_MASK 0x01FFFFFF //----------------------------------- #define CFG_LEDC1_TARGET_CONF_ADDR 0x0060 #define LEDC1_TARGET_SHADOW_EN_OFFSET 31 #define LEDC1_TARGET_SHADOW_EN_MASK 0x80000000 #define LEDC1_TARGET_INC_OR_DEC_OFFSET 30 #define LEDC1_TARGET_INC_OR_DEC_MASK 0x40000000 #define LEDC1_TARGET_INC_OR_DEC_NUM_OFFSET 20 #define LEDC1_TARGET_INC_OR_DEC_NUM_MASK 0x3FF00000 #define LEDC1_TARGET_INC_OR_DEC_CYCLE_OFFSET 10 #define LEDC1_TARGET_INC_OR_DEC_CYCLE_MASK 0x000FFC00 #define LEDC1_TARGET_INC_OR_DEC_SCOPE_OFFSET 0 #define LEDC1_TARGET_INC_OR_DEC_SCOPE_MASK 0x000003FF //----------------------------------- #define CFG_LEDC1_READ_TARGET_VALUE_ADDR 0x0064 #define LEDC1_READ_TARGET_OFFSET 0 #define LEDC1_READ_TARGET_MASK 0x01FFFFFF //----------------------------------- #define CFG_LEDC2_CONF_ADDR 0x0068 #define LEDC2_SIGOUT_SEL_OFFSET 4 #define LEDC2_SIGOUT_SEL_MASK 0x00000010 #define LEDC2_SIGOUT_IDLE_VALUE_OFFSET 3 #define LEDC2_SIGOUT_IDLE_VALUE_MASK 0x00000008 #define LEDC2_SIGOUT_EB_OFFSET 2 #define LEDC2_SIGOUT_EB_MASK 0x00000004 #define LEDC2_TIMER_SEL_OFFSET 0 #define LEDC2_TIMER_SEL_MASK 0x00000003 //----------------------------------- #define CFG_LEDC2_L2H_VALUE_ADDR 0x006C #define LEDC2_L2H_VALUE_OFFSET 0 #define LEDC2_L2H_VALUE_MASK 0x000FFFFF //----------------------------------- #define CFG_LEDC2_TARGET_VALUE_ADDR 0x0070 #define LEDC2_TARGET_VALUE_OFFSET 0 #define LEDC2_TARGET_VALUE_MASK 0x01FFFFFF //----------------------------------- #define CFG_LEDC2_TARGET_CONF_ADDR 0x0074 #define LEDC2_TARGET_SHADOW_EN_OFFSET 31 #define LEDC2_TARGET_SHADOW_EN_MASK 0x80000000 #define LEDC2_TARGET_INC_OR_DEC_OFFSET 30 #define LEDC2_TARGET_INC_OR_DEC_MASK 0x40000000 #define LEDC2_TARGET_INC_OR_DEC_NUM_OFFSET 20 #define LEDC2_TARGET_INC_OR_DEC_NUM_MASK 0x3FF00000 #define LEDC2_TARGET_INC_OR_DEC_CYCLE_OFFSET 10 #define LEDC2_TARGET_INC_OR_DEC_CYCLE_MASK 0x000FFC00 #define LEDC2_TARGET_INC_OR_DEC_SCOPE_OFFSET 0 #define LEDC2_TARGET_INC_OR_DEC_SCOPE_MASK 0x000003FF //----------------------------------- #define CFG_LEDC2_READ_TARGET_VALUE_ADDR 0x0078 #define LEDC2_READ_TARGET_OFFSET 0 #define LEDC2_READ_TARGET_MASK 0x01FFFFFF //----------------------------------- #define CFG_LEDC3_CONF_ADDR 0x007C #define LEDC3_SIGOUT_SEL_OFFSET 4 #define LEDC3_SIGOUT_SEL_MASK 0x00000010 #define LEDC3_SIGOUT_IDLE_VALUE_OFFSET 3 #define LEDC3_SIGOUT_IDLE_VALUE_MASK 0x00000008 #define LEDC3_SIGOUT_EB_OFFSET 2 #define LEDC3_SIGOUT_EB_MASK 0x00000004 #define LEDC3_TIMER_SEL_OFFSET 0 #define LEDC3_TIMER_SEL_MASK 0x00000003 //----------------------------------- #define CFG_LEDC3_L2H_VALUE_ADDR 0x0080 #define LEDC3_L2H_VALUE_OFFSET 0 #define LEDC3_L2H_VALUE_MASK 0x000FFFFF //----------------------------------- #define CFG_LEDC3_TARGET_VALUE_ADDR 0x0084 #define LEDC3_TARGET_VALUE_OFFSET 0 #define LEDC3_TARGET_VALUE_MASK 0x01FFFFFF //----------------------------------- #define CFG_LEDC3_TARGET_CONF_ADDR 0x0088 #define LEDC3_TARGET_SHADOW_EN_OFFSET 31 #define LEDC3_TARGET_SHADOW_EN_MASK 0x80000000 #define LEDC3_TARGET_INC_OR_DEC_OFFSET 30 #define LEDC3_TARGET_INC_OR_DEC_MASK 0x40000000 #define LEDC3_TARGET_INC_OR_DEC_NUM_OFFSET 20 #define LEDC3_TARGET_INC_OR_DEC_NUM_MASK 0x3FF00000 #define LEDC3_TARGET_INC_OR_DEC_CYCLE_OFFSET 10 #define LEDC3_TARGET_INC_OR_DEC_CYCLE_MASK 0x000FFC00 #define LEDC3_TARGET_INC_OR_DEC_SCOPE_OFFSET 0 #define LEDC3_TARGET_INC_OR_DEC_SCOPE_MASK 0x000003FF //----------------------------------- #define CFG_LEDC3_READ_TARGET_VALUE_ADDR 0x008C #define LEDC3_READ_TARGET_OFFSET 0 #define LEDC3_READ_TARGET_MASK 0x01FFFFFF //----------------------------------- #define CFG_LEDC4_CONF_ADDR 0x0090 #define LEDC4_SIGOUT_SEL_OFFSET 4 #define LEDC4_SIGOUT_SEL_MASK 0x00000010 #define LEDC4_SIGOUT_IDLE_VALUE_OFFSET 3 #define LEDC4_SIGOUT_IDLE_VALUE_MASK 0x00000008 #define LEDC4_SIGOUT_EB_OFFSET 2 #define LEDC4_SIGOUT_EB_MASK 0x00000004 #define LEDC4_TIMER_SEL_OFFSET 0 #define LEDC4_TIMER_SEL_MASK 0x00000003 //----------------------------------- #define CFG_LEDC4_L2H_VALUE_ADDR 0x0094 #define LEDC4_L2H_VALUE_OFFSET 0 #define LEDC4_L2H_VALUE_MASK 0x000FFFFF //----------------------------------- #define CFG_LEDC4_TARGET_VALUE_ADDR 0x0098 #define LEDC4_TARGET_VALUE_OFFSET 0 #define LEDC4_TARGET_VALUE_MASK 0x01FFFFFF //----------------------------------- #define CFG_LEDC4_TARGET_CONF_ADDR 0x009C #define LEDC4_TARGET_SHADOW_EN_OFFSET 31 #define LEDC4_TARGET_SHADOW_EN_MASK 0x80000000 #define LEDC4_TARGET_INC_OR_DEC_OFFSET 30 #define LEDC4_TARGET_INC_OR_DEC_MASK 0x40000000 #define LEDC4_TARGET_INC_OR_DEC_NUM_OFFSET 20 #define LEDC4_TARGET_INC_OR_DEC_NUM_MASK 0x3FF00000 #define LEDC4_TARGET_INC_OR_DEC_CYCLE_OFFSET 10 #define LEDC4_TARGET_INC_OR_DEC_CYCLE_MASK 0x000FFC00 #define LEDC4_TARGET_INC_OR_DEC_SCOPE_OFFSET 0 #define LEDC4_TARGET_INC_OR_DEC_SCOPE_MASK 0x000003FF //----------------------------------- #define CFG_LEDC4_READ_TARGET_VALUE_ADDR 0x00A0 #define LEDC4_READ_TARGET_OFFSET 0 #define LEDC4_READ_TARGET_MASK 0x01FFFFFF //----------------------------------- #define CFG_LEDC5_CONF_ADDR 0x00A4 #define LEDC5_SIGOUT_SEL_OFFSET 4 #define LEDC5_SIGOUT_SEL_MASK 0x00000010 #define LEDC5_SIGOUT_IDLE_VALUE_OFFSET 3 #define LEDC5_SIGOUT_IDLE_VALUE_MASK 0x00000008 #define LEDC5_SIGOUT_EB_OFFSET 2 #define LEDC5_SIGOUT_EB_MASK 0x00000004 #define LEDC5_TIMER_SEL_OFFSET 0 #define LEDC5_TIMER_SEL_MASK 0x00000003 //----------------------------------- #define CFG_LEDC5_L2H_VALUE_ADDR 0x00A8 #define LEDC5_L2H_VALUE_OFFSET 0 #define LEDC5_L2H_VALUE_MASK 0x000FFFFF //----------------------------------- #define CFG_LEDC5_TARGET_VALUE_ADDR 0x00AC #define LEDC5_TARGET_VALUE_OFFSET 0 #define LEDC5_TARGET_VALUE_MASK 0x01FFFFFF //----------------------------------- #define CFG_LEDC5_TARGET_CONF_ADDR 0x00B0 #define LEDC5_TARGET_SHADOW_EN_OFFSET 31 #define LEDC5_TARGET_SHADOW_EN_MASK 0x80000000 #define LEDC5_TARGET_INC_OR_DEC_OFFSET 30 #define LEDC5_TARGET_INC_OR_DEC_MASK 0x40000000 #define LEDC5_TARGET_INC_OR_DEC_NUM_OFFSET 20 #define LEDC5_TARGET_INC_OR_DEC_NUM_MASK 0x3FF00000 #define LEDC5_TARGET_INC_OR_DEC_CYCLE_OFFSET 10 #define LEDC5_TARGET_INC_OR_DEC_CYCLE_MASK 0x000FFC00 #define LEDC5_TARGET_INC_OR_DEC_SCOPE_OFFSET 0 #define LEDC5_TARGET_INC_OR_DEC_SCOPE_MASK 0x000003FF //----------------------------------- #define CFG_LEDC5_READ_TARGET_VALUE_ADDR 0x00B4 #define LEDC5_READ_TARGET_OFFSET 0 #define LEDC5_READ_TARGET_MASK 0x01FFFFFF //----------------------------------- #define CFG_LEDC6_CONF_ADDR 0x00B8 #define LEDC6_SIGOUT_SEL_OFFSET 4 #define LEDC6_SIGOUT_SEL_MASK 0x00000010 #define LEDC6_SIGOUT_IDLE_VALUE_OFFSET 3 #define LEDC6_SIGOUT_IDLE_VALUE_MASK 0x00000008 #define LEDC6_SIGOUT_EB_OFFSET 2 #define LEDC6_SIGOUT_EB_MASK 0x00000004 #define LEDC6_TIMER_SEL_OFFSET 0 #define LEDC6_TIMER_SEL_MASK 0x00000003 //----------------------------------- #define CFG_LEDC6_L2H_VALUE_ADDR 0x00BC #define LEDC6_L2H_VALUE_OFFSET 0 #define LEDC6_L2H_VALUE_MASK 0x000FFFFF //----------------------------------- #define CFG_LEDC6_TARGET_VALUE_ADDR 0x00C0 #define LEDC6_TARGET_VALUE_OFFSET 0 #define LEDC6_TARGET_VALUE_MASK 0x01FFFFFF //----------------------------------- #define CFG_LEDC6_TARGET_CONF_ADDR 0x00C4 #define LEDC6_TARGET_SHADOW_EN_OFFSET 31 #define LEDC6_TARGET_SHADOW_EN_MASK 0x80000000 #define LEDC6_TARGET_INC_OR_DEC_OFFSET 30 #define LEDC6_TARGET_INC_OR_DEC_MASK 0x40000000 #define LEDC6_TARGET_INC_OR_DEC_NUM_OFFSET 20 #define LEDC6_TARGET_INC_OR_DEC_NUM_MASK 0x3FF00000 #define LEDC6_TARGET_INC_OR_DEC_CYCLE_OFFSET 10 #define LEDC6_TARGET_INC_OR_DEC_CYCLE_MASK 0x000FFC00 #define LEDC6_TARGET_INC_OR_DEC_SCOPE_OFFSET 0 #define LEDC6_TARGET_INC_OR_DEC_SCOPE_MASK 0x000003FF //----------------------------------- #define CFG_LEDC6_READ_TARGET_VALUE_ADDR 0x00C8 #define LEDC6_READ_TARGET_OFFSET 0 #define LEDC6_READ_TARGET_MASK 0x01FFFFFF //----------------------------------- #define CFG_LEDC7_CONF_ADDR 0x00CC #define LEDC7_SIGOUT_SEL_OFFSET 4 #define LEDC7_SIGOUT_SEL_MASK 0x00000010 #define LEDC7_SIGOUT_IDLE_VALUE_OFFSET 3 #define LEDC7_SIGOUT_IDLE_VALUE_MASK 0x00000008 #define LEDC7_SIGOUT_EB_OFFSET 2 #define LEDC7_SIGOUT_EB_MASK 0x00000004 #define LEDC7_TIMER_SEL_OFFSET 0 #define LEDC7_TIMER_SEL_MASK 0x00000003 //----------------------------------- #define CFG_LEDC7_L2H_VALUE_ADDR 0x00D0 #define LEDC7_L2H_VALUE_OFFSET 0 #define LEDC7_L2H_VALUE_MASK 0x000FFFFF //----------------------------------- #define CFG_LEDC7_TARGET_VALUE_ADDR 0x00D4 #define LEDC7_TARGET_VALUE_OFFSET 0 #define LEDC7_TARGET_VALUE_MASK 0x01FFFFFF //----------------------------------- #define CFG_LEDC7_TARGET_CONF_ADDR 0x00D8 #define LEDC7_TARGET_SHADOW_EN_OFFSET 31 #define LEDC7_TARGET_SHADOW_EN_MASK 0x80000000 #define LEDC7_TARGET_INC_OR_DEC_OFFSET 30 #define LEDC7_TARGET_INC_OR_DEC_MASK 0x40000000 #define LEDC7_TARGET_INC_OR_DEC_NUM_OFFSET 20 #define LEDC7_TARGET_INC_OR_DEC_NUM_MASK 0x3FF00000 #define LEDC7_TARGET_INC_OR_DEC_CYCLE_OFFSET 10 #define LEDC7_TARGET_INC_OR_DEC_CYCLE_MASK 0x000FFC00 #define LEDC7_TARGET_INC_OR_DEC_SCOPE_OFFSET 0 #define LEDC7_TARGET_INC_OR_DEC_SCOPE_MASK 0x000003FF //----------------------------------- #define CFG_LEDC7_READ_TARGET_VALUE_ADDR 0x00DC #define LEDC7_READ_TARGET_OFFSET 0 #define LEDC7_READ_TARGET_MASK 0x01FFFFFF //----------------------------------- #define CFG_LEDC8_CONF_ADDR 0x00E0 #define LEDC8_SIGOUT_IDLE_VALUE_OFFSET 3 #define LEDC8_SIGOUT_IDLE_VALUE_MASK 0x00000008 #define LEDC8_SIGOUT_EB_OFFSET 2 #define LEDC8_SIGOUT_EB_MASK 0x00000004 #define LEDC8_TIMER_SEL_OFFSET 0 #define LEDC8_TIMER_SEL_MASK 0x00000003 //----------------------------------- #define CFG_LEDC8_L2H_VALUE_ADDR 0x00E4 #define LEDC8_L2H_VALUE_OFFSET 0 #define LEDC8_L2H_VALUE_MASK 0x000FFFFF //----------------------------------- #define CFG_LEDC8_TARGET_VALUE_ADDR 0x00E8 #define LEDC8_TARGET_VALUE_OFFSET 0 #define LEDC8_TARGET_VALUE_MASK 0x01FFFFFF //----------------------------------- #define CFG_LEDC8_TARGET_CONF_ADDR 0x00EC #define LEDC8_TARGET_SHADOW_EN_OFFSET 31 #define LEDC8_TARGET_SHADOW_EN_MASK 0x80000000 #define LEDC8_TARGET_INC_OR_DEC_OFFSET 30 #define LEDC8_TARGET_INC_OR_DEC_MASK 0x40000000 #define LEDC8_TARGET_INC_OR_DEC_NUM_OFFSET 20 #define LEDC8_TARGET_INC_OR_DEC_NUM_MASK 0x3FF00000 #define LEDC8_TARGET_INC_OR_DEC_CYCLE_OFFSET 10 #define LEDC8_TARGET_INC_OR_DEC_CYCLE_MASK 0x000FFC00 #define LEDC8_TARGET_INC_OR_DEC_SCOPE_OFFSET 0 #define LEDC8_TARGET_INC_OR_DEC_SCOPE_MASK 0x000003FF //----------------------------------- #define CFG_LEDC8_READ_TARGET_VALUE_ADDR 0x00F0 #define LEDC8_READ_TARGET_OFFSET 0 #define LEDC8_READ_TARGET_MASK 0x01FFFFFF //----------------------------------- #define CFG_LEDC_TIMER0_CONF_ADDR 0x0000 #define TIMER0_TICK_REF_SEL_OFFSET 31 #define TIMER0_TICK_REF_SEL_MASK 0x80000000 #define TIMER0_INIT_OFFSET 30 #define TIMER0_INIT_MASK 0x40000000 #define TIMER0_PAUSE_EN_OFFSET 29 #define TIMER0_PAUSE_EN_MASK 0x20000000 #define TIMER0_DIV_OFFSET 5 #define TIMER0_DIV_MASK 0x1FFFFFE0 #define TIMER0_UPLIM_OFFSET 0 #define TIMER0_UPLIM_MASK 0x0000001F //----------------------------------- #define CFG_LEDC_TIMER0_VALUE_ADDR 0x0004 #define TIMER0_CNT_VALUE_OFFSET 0 #define TIMER0_CNT_VALUE_MASK 0x000FFFFF //----------------------------------- #define CFG_LEDC_TIMER1_CONF_ADDR 0x0008 #define TIMER1_TICK_REF_SEL_OFFSET 31 #define TIMER1_TICK_REF_SEL_MASK 0x80000000 #define TIMER1_INIT_OFFSET 30 #define TIMER1_INIT_MASK 0x40000000 #define TIMER1_PAUSE_EN_OFFSET 29 #define TIMER1_PAUSE_EN_MASK 0x20000000 #define TIMER1_DIV_OFFSET 5 #define TIMER1_DIV_MASK 0x1FFFFFE0 #define TIMER1_UPLIM_OFFSET 0 #define TIMER1_UPLIM_MASK 0x0000001F //----------------------------------- #define CFG_LEDC_TIMER1_VALUE_ADDR 0x000C #define TIMER1_CNT_VALUE_OFFSET 0 #define TIMER1_CNT_VALUE_MASK 0x000FFFFF //----------------------------------- #define CFG_LEDC_TIMER2_CONF_ADDR 0x0010 #define TIMER2_TICK_REF_SEL_OFFSET 31 #define TIMER2_TICK_REF_SEL_MASK 0x80000000 #define TIMER2_INIT_OFFSET 30 #define TIMER2_INIT_MASK 0x40000000 #define TIMER2_PAUSE_EN_OFFSET 29 #define TIMER2_PAUSE_EN_MASK 0x20000000 #define TIMER2_DIV_OFFSET 5 #define TIMER2_DIV_MASK 0x1FFFFFE0 #define TIMER2_UPLIM_OFFSET 0 #define TIMER2_UPLIM_MASK 0x0000001F //----------------------------------- #define CFG_LEDC_TIMER2_VALUE_ADDR 0x0014 #define TIMER2_CNT_VALUE_OFFSET 0 #define TIMER2_CNT_VALUE_MASK 0x000FFFFF //----------------------------------- #define CFG_LEDC_TIMER3_CONF_ADDR 0x0018 #define TIMER3_TICK_REF_SEL_OFFSET 31 #define TIMER3_TICK_REF_SEL_MASK 0x80000000 #define TIMER3_INIT_OFFSET 30 #define TIMER3_INIT_MASK 0x40000000 #define TIMER3_PAUSE_EN_OFFSET 29 #define TIMER3_PAUSE_EN_MASK 0x20000000 #define TIMER3_DIV_OFFSET 5 #define TIMER3_DIV_MASK 0x1FFFFFE0 #define TIMER3_UPLIM_OFFSET 0 #define TIMER3_UPLIM_MASK 0x0000001F //----------------------------------- #define CFG_LEDC_TIMER3_VALUE_ADDR 0x001C #define TIMER3_CNT_VALUE_OFFSET 0 #define TIMER3_CNT_VALUE_MASK 0x000FFFFF //----------------------------------- #define CFG_LEDC_INT_RAW_ADDR 0x0020 #define TARGET_CHANGE_END_LEDC7_INT_RAW_OFFSET 11 #define TARGET_CHANGE_END_LEDC7_INT_RAW_MASK 0x00000800 #define TARGET_CHANGE_END_LEDC6_INT_RAW_OFFSET 10 #define TARGET_CHANGE_END_LEDC6_INT_RAW_MASK 0x00000400 #define TARGET_CHANGE_END_LEDC5_INT_RAW_OFFSET 9 #define TARGET_CHANGE_END_LEDC5_INT_RAW_MASK 0x00000200 #define TARGET_CHANGE_END_LEDC4_INT_RAW_OFFSET 8 #define TARGET_CHANGE_END_LEDC4_INT_RAW_MASK 0x00000100 #define TARGET_CHANGE_END_LEDC3_INT_RAW_OFFSET 7 #define TARGET_CHANGE_END_LEDC3_INT_RAW_MASK 0x00000080 #define TARGET_CHANGE_END_LEDC2_INT_RAW_OFFSET 6 #define TARGET_CHANGE_END_LEDC2_INT_RAW_MASK 0x00000040 #define TARGET_CHANGE_END_LEDC1_INT_RAW_OFFSET 5 #define TARGET_CHANGE_END_LEDC1_INT_RAW_MASK 0x00000020 #define TARGET_CHANGE_END_LEDC0_INT_RAW_OFFSET 4 #define TARGET_CHANGE_END_LEDC0_INT_RAW_MASK 0x00000010 #define TIMER3_OVF_INT_RAW_OFFSET 3 #define TIMER3_OVF_INT_RAW_MASK 0x00000008 #define TIMER2_OVF_INT_RAW_OFFSET 2 #define TIMER2_OVF_INT_RAW_MASK 0x00000004 #define TIMER1_OVF_INT_RAW_OFFSET 1 #define TIMER1_OVF_INT_RAW_MASK 0x00000002 #define TIMER0_OVF_INT_RAW_OFFSET 0 #define TIMER0_OVF_INT_RAW_MASK 0x00000001 //----------------------------------- #define CFG_LEDC_INT_ST_ADDR 0x0024 #define TARGET_CHANGE_END_LEDC7_INT_ST_OFFSET 11 #define TARGET_CHANGE_END_LEDC7_INT_ST_MASK 0x00000800 #define TARGET_CHANGE_END_LEDC6_INT_ST_OFFSET 10 #define TARGET_CHANGE_END_LEDC6_INT_ST_MASK 0x00000400 #define TARGET_CHANGE_END_LEDC5_INT_ST_OFFSET 9 #define TARGET_CHANGE_END_LEDC5_INT_ST_MASK 0x00000200 #define TARGET_CHANGE_END_LEDC4_INT_ST_OFFSET 8 #define TARGET_CHANGE_END_LEDC4_INT_ST_MASK 0x00000100 #define TARGET_CHANGE_END_LEDC3_INT_ST_OFFSET 7 #define TARGET_CHANGE_END_LEDC3_INT_ST_MASK 0x00000080 #define TARGET_CHANGE_END_LEDC2_INT_ST_OFFSET 6 #define TARGET_CHANGE_END_LEDC2_INT_ST_MASK 0x00000040 #define TARGET_CHANGE_END_LEDC1_INT_ST_OFFSET 5 #define TARGET_CHANGE_END_LEDC1_INT_ST_MASK 0x00000020 #define TARGET_CHANGE_END_LEDC0_INT_ST_OFFSET 4 #define TARGET_CHANGE_END_LEDC0_INT_ST_MASK 0x00000010 #define TIMER3_OVF_INT_ST_OFFSET 3 #define TIMER3_OVF_INT_ST_MASK 0x00000008 #define TIMER2_OVF_INT_ST_OFFSET 2 #define TIMER2_OVF_INT_ST_MASK 0x00000004 #define TIMER1_OVF_INT_ST_OFFSET 1 #define TIMER1_OVF_INT_ST_MASK 0x00000002 #define TIMER0_OVF_INT_ST_OFFSET 0 #define TIMER0_OVF_INT_ST_MASK 0x00000001 //----------------------------------- #define CFG_LEDC_INT_ENA_ADDR 0x0028 #define TARGET_CHANGE_END_LEDC7_INT_ENA_OFFSET 11 #define TARGET_CHANGE_END_LEDC7_INT_ENA_MASK 0x00000800 #define TARGET_CHANGE_END_LEDC6_INT_ENA_OFFSET 10 #define TARGET_CHANGE_END_LEDC6_INT_ENA_MASK 0x00000400 #define TARGET_CHANGE_END_LEDC5_INT_ENA_OFFSET 9 #define TARGET_CHANGE_END_LEDC5_INT_ENA_MASK 0x00000200 #define TARGET_CHANGE_END_LEDC4_INT_ENA_OFFSET 8 #define TARGET_CHANGE_END_LEDC4_INT_ENA_MASK 0x00000100 #define TARGET_CHANGE_END_LEDC3_INT_ENA_OFFSET 7 #define TARGET_CHANGE_END_LEDC3_INT_ENA_MASK 0x00000080 #define TARGET_CHANGE_END_LEDC2_INT_ENA_OFFSET 6 #define TARGET_CHANGE_END_LEDC2_INT_ENA_MASK 0x00000040 #define TARGET_CHANGE_END_LEDC1_INT_ENA_OFFSET 5 #define TARGET_CHANGE_END_LEDC1_INT_ENA_MASK 0x00000020 #define TARGET_CHANGE_END_LEDC0_INT_ENA_OFFSET 4 #define TARGET_CHANGE_END_LEDC0_INT_ENA_MASK 0x00000010 #define TIMER3_OVF_INT_ENA_OFFSET 3 #define TIMER3_OVF_INT_ENA_MASK 0x00000008 #define TIMER2_OVF_INT_ENA_OFFSET 2 #define TIMER2_OVF_INT_ENA_MASK 0x00000004 #define TIMER1_OVF_INT_ENA_OFFSET 1 #define TIMER1_OVF_INT_ENA_MASK 0x00000002 #define TIMER0_OVF_INT_ENA_OFFSET 0 #define TIMER0_OVF_INT_ENA_MASK 0x00000001 //----------------------------------- #define CFG_LEDC_INT_CLR_ADDR 0x002C #define TARGET_CHANGE_END_LEDC7_INT_CLR_OFFSET 11 #define TARGET_CHANGE_END_LEDC7_INT_CLR_MASK 0x00000800 #define TARGET_CHANGE_END_LEDC6_INT_CLR_OFFSET 10 #define TARGET_CHANGE_END_LEDC6_INT_CLR_MASK 0x00000400 #define TARGET_CHANGE_END_LEDC5_INT_CLR_OFFSET 9 #define TARGET_CHANGE_END_LEDC5_INT_CLR_MASK 0x00000200 #define TARGET_CHANGE_END_LEDC4_INT_CLR_OFFSET 8 #define TARGET_CHANGE_END_LEDC4_INT_CLR_MASK 0x00000100 #define TARGET_CHANGE_END_LEDC3_INT_CLR_OFFSET 7 #define TARGET_CHANGE_END_LEDC3_INT_CLR_MASK 0x00000080 #define TARGET_CHANGE_END_LEDC2_INT_CLR_OFFSET 6 #define TARGET_CHANGE_END_LEDC2_INT_CLR_MASK 0x00000040 #define TARGET_CHANGE_END_LEDC1_INT_CLR_OFFSET 5 #define TARGET_CHANGE_END_LEDC1_INT_CLR_MASK 0x00000020 #define TARGET_CHANGE_END_LEDC0_INT_CLR_OFFSET 4 #define TARGET_CHANGE_END_LEDC0_INT_CLR_MASK 0x00000010 #define TIMER3_OVF_INT_CLR_OFFSET 3 #define TIMER3_OVF_INT_CLR_MASK 0x00000008 #define TIMER2_OVF_INT_CLR_OFFSET 2 #define TIMER2_OVF_INT_CLR_MASK 0x00000004 #define TIMER1_OVF_INT_CLR_OFFSET 1 #define TIMER1_OVF_INT_CLR_MASK 0x00000002 #define TIMER0_OVF_INT_CLR_OFFSET 0 #define TIMER0_OVF_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_LEDC_DATE_ADDR 0x0030 #define LEDC_DATE_OFFSET 0 #define LEDC_DATE_MASK 0xFFFFFFFF //----------------------------------- #define CFG_LEDC8_PHASE_CONF_ADDR 0x0034 #define REG_IDLE_SRC_VAL_OFFSET 24 #define REG_IDLE_SRC_VAL_MASK 0x07000000 #define LEDC0_PHASE7_OFFSET 21 #define LEDC0_PHASE7_MASK 0x00E00000 #define LEDC0_PHASE6_OFFSET 18 #define LEDC0_PHASE6_MASK 0x001C0000 #define LEDC0_PHASE5_OFFSET 15 #define LEDC0_PHASE5_MASK 0x00038000 #define LEDC0_PHASE4_OFFSET 12 #define LEDC0_PHASE4_MASK 0x00007000 #define LEDC0_PHASE3_OFFSET 9 #define LEDC0_PHASE3_MASK 0x00000E00 #define LEDC0_PHASE2_OFFSET 6 #define LEDC0_PHASE2_MASK 0x000001C0 #define LEDC0_PHASE1_OFFSET 3 #define LEDC0_PHASE1_MASK 0x00000038 #define LEDC0_PHASE0_OFFSET 0 #define LEDC0_PHASE0_MASK 0x00000007 //HW module read/write macro #define LEDC_READ_REG(addr) SOC_READ_REG(LEDC_BASEADDR + addr) #define LEDC_WRITE_REG(addr,value) SOC_WRITE_REG(LEDC_BASEADDR + addr,value)