//-----------------------------------
#define CFG_MSG0_STS_ADDR 0x0000
#define FIFO0_EMPTY_OFFSET 9
#define FIFO0_EMPTY_MASK 0x00000200
#define FIFO0_FULL_OFFSET 8
#define FIFO0_FULL_MASK 0x00000100
#define FIFO0_DATA_NUM_OFFSET 0
#define FIFO0_DATA_NUM_MASK 0x0000003F

//-----------------------------------
#define CFG_MSG0_RCTRL_ADDR 0x0004
#define FIFO0_READ_OFFSET 0
#define FIFO0_READ_MASK 0x00000001

//-----------------------------------
#define CFG_MSG0_RDATA_ADDR 0x0008
#define FIFO0_READ_DATA_OFFSET 0
#define FIFO0_READ_DATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MSG0_WDATA_ADDR 0x000C
#define FIFO0_WDATA_OFFSET 0
#define FIFO0_WDATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MSG1_STS_ADDR 0x0010
#define FIFO1_EMPTY_OFFSET 9
#define FIFO1_EMPTY_MASK 0x00000200
#define FIFO1_FULL_OFFSET 8
#define FIFO1_FULL_MASK 0x00000100
#define FIFO1_DATA_NUM_OFFSET 0
#define FIFO1_DATA_NUM_MASK 0x0000003F

//-----------------------------------
#define CFG_MSG1_RCTRL_ADDR 0x0014
#define FIFO1_READ_OFFSET 0
#define FIFO1_READ_MASK 0x00000001

//-----------------------------------
#define CFG_MSG1_RDATA_ADDR 0x0018
#define FIFO1_READ_DATA_OFFSET 0
#define FIFO1_READ_DATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MSG1_WDATA_ADDR 0x001C
#define FIFO1_WDATA_OFFSET 0
#define FIFO1_WDATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MSG2_STS_ADDR 0x0020
#define FIFO2_EMPTY_OFFSET 9
#define FIFO2_EMPTY_MASK 0x00000200
#define FIFO2_FULL_OFFSET 8
#define FIFO2_FULL_MASK 0x00000100
#define FIFO2_DATA_NUM_OFFSET 0
#define FIFO2_DATA_NUM_MASK 0x0000003F

//-----------------------------------
#define CFG_MSG2_RCTRL_ADDR 0x0024
#define FIFO2_READ_OFFSET 0
#define FIFO2_READ_MASK 0x00000001

//-----------------------------------
#define CFG_MSG2_RDATA_ADDR 0x0028
#define FIFO2_READ_DATA_OFFSET 0
#define FIFO2_READ_DATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MSG2_WDATA_ADDR 0x002C
#define FIFO2_WDATA_OFFSET 0
#define FIFO2_WDATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MSG3_STS_ADDR 0x0030
#define FIFO3_EMPTY_OFFSET 9
#define FIFO3_EMPTY_MASK 0x00000200
#define FIFO3_FULL_OFFSET 8
#define FIFO3_FULL_MASK 0x00000100
#define FIFO3_DATA_NUM_OFFSET 0
#define FIFO3_DATA_NUM_MASK 0x0000003F

//-----------------------------------
#define CFG_MSG3_RCTRL_ADDR 0x0034
#define FIFO3_READ_OFFSET 0
#define FIFO3_READ_MASK 0x00000001

//-----------------------------------
#define CFG_MSG3_RDATA_ADDR 0x0038
#define FIFO3_READ_DATA_OFFSET 0
#define FIFO3_READ_DATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MSG3_WDATA_ADDR 0x003C
#define FIFO3_WDATA_OFFSET 0
#define FIFO3_WDATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MSG4_STS_ADDR 0x0040
#define FIFO4_EMPTY_OFFSET 9
#define FIFO4_EMPTY_MASK 0x00000200
#define FIFO4_FULL_OFFSET 8
#define FIFO4_FULL_MASK 0x00000100
#define FIFO4_DATA_NUM_OFFSET 0
#define FIFO4_DATA_NUM_MASK 0x0000003F

//-----------------------------------
#define CFG_MSG4_RCTRL_ADDR 0x0044
#define FIFO4_READ_OFFSET 0
#define FIFO4_READ_MASK 0x00000001

//-----------------------------------
#define CFG_MSG4_RDATA_ADDR 0x0048
#define FIFO4_READ_DATA_OFFSET 0
#define FIFO4_READ_DATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MSG4_WDATA_ADDR 0x004C
#define FIFO4_WDATA_OFFSET 0
#define FIFO4_WDATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MSG5_STS_ADDR 0x0050
#define FIFO5_EMPTY_OFFSET 9
#define FIFO5_EMPTY_MASK 0x00000200
#define FIFO5_FULL_OFFSET 8
#define FIFO5_FULL_MASK 0x00000100
#define FIFO5_DATA_NUM_OFFSET 0
#define FIFO5_DATA_NUM_MASK 0x0000003F

//-----------------------------------
#define CFG_MSG5_RCTRL_ADDR 0x0054
#define FIFO5_READ_OFFSET 0
#define FIFO5_READ_MASK 0x00000001

//-----------------------------------
#define CFG_MSG5_RDATA_ADDR 0x0058
#define FIFO5_READ_DATA_OFFSET 0
#define FIFO5_READ_DATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MSG5_WDATA_ADDR 0x005C
#define FIFO5_WDATA_OFFSET 0
#define FIFO5_WDATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MSG6_STS_ADDR 0x0060
#define FIFO6_EMPTY_OFFSET 9
#define FIFO6_EMPTY_MASK 0x00000200
#define FIFO6_FULL_OFFSET 8
#define FIFO6_FULL_MASK 0x00000100
#define FIFO6_DATA_NUM_OFFSET 0
#define FIFO6_DATA_NUM_MASK 0x0000003F

//-----------------------------------
#define CFG_MSG6_RCTRL_ADDR 0x0064
#define FIFO6_READ_OFFSET 0
#define FIFO6_READ_MASK 0x00000001

//-----------------------------------
#define CFG_MSG6_RDATA_ADDR 0x0068
#define FIFO6_READ_DATA_OFFSET 0
#define FIFO6_READ_DATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MSG6_WDATA_ADDR 0x006C
#define FIFO6_WDATA_OFFSET 0
#define FIFO6_WDATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MSG7_STS_ADDR 0x0070
#define FIFO7_EMPTY_OFFSET 9
#define FIFO7_EMPTY_MASK 0x00000200
#define FIFO7_FULL_OFFSET 8
#define FIFO7_FULL_MASK 0x00000100
#define FIFO7_DATA_NUM_OFFSET 0
#define FIFO7_DATA_NUM_MASK 0x0000003F

//-----------------------------------
#define CFG_MSG7_RCTRL_ADDR 0x0074
#define FIFO7_READ_OFFSET 0
#define FIFO7_READ_MASK 0x00000001

//-----------------------------------
#define CFG_MSG7_RDATA_ADDR 0x0078
#define FIFO7_READ_DATA_OFFSET 0
#define FIFO7_READ_DATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MSG7_WDATA_ADDR 0x007C
#define FIFO7_WDATA_OFFSET 0
#define FIFO7_WDATA_MASK 0xFFFFFFFF

//HW module read/write macro
#define MAIL_BOX_NEW_RF_READ_REG(addr) SOC_READ_REG(MAIL_BOX_NEW_RF_BASEADDR + addr)
#define MAIL_BOX_NEW_RF_WRITE_REG(addr,value) SOC_WRITE_REG(MAIL_BOX_NEW_RF_BASEADDR + addr,value)