//----------------------------------- #define CFG_NDFC_RVER_ADDR 0x0000 #define NDFC_RF_VER_OFFSET 0 #define NDFC_RF_VER_MASK 0x0000FFFF //----------------------------------- #define CFG_NDFC_CMD0_ADDR 0x0004 #define SW_NDFC_ENA_OFFSET 31 #define SW_NDFC_ENA_MASK 0x80000000 #define SW_NDFC_DLEN_OFFSET 16 #define SW_NDFC_DLEN_MASK 0x0FFF0000 #define SW_NDFC_CMODE_OFFSET 8 #define SW_NDFC_CMODE_MASK 0x0000FF00 #define SW_NDFC_RD_NUM_OFFSET 5 #define SW_NDFC_RD_NUM_MASK 0x000000E0 #define SW_NDFC_DATA_WR_OFFSET 4 #define SW_NDFC_DATA_WR_MASK 0x00000010 #define SW_NDFC_MODE_OFFSET 1 #define SW_NDFC_MODE_MASK 0x0000000E #define CFG_NDFC_EXT_SEL_OFFSET 0 #define CFG_NDFC_EXT_SEL_MASK 0x00000001 //----------------------------------- #define CFG_NDFC_CMD1_ADDR 0x0008 #define SW_NDFC_CMD_OFFSET 24 #define SW_NDFC_CMD_MASK 0xFF000000 //----------------------------------- #define CFG_NDFC_CTRL0_ADDR 0x000c #define NDFC_SW_FORCE_MODE_OFFSET 31 #define NDFC_SW_FORCE_MODE_MASK 0x80000000 #define CFG_NDFC_PAGE_SIZE_OFFSET 0 #define CFG_NDFC_PAGE_SIZE_MASK 0x00000FFF //----------------------------------- #define CFG_NDFC_CMD2_ADDR 0x0010 #define SW_DMA_START_ADDR_OFFSET 0 #define SW_DMA_START_ADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_CMD3_ADDR 0x0014 #define SW_NDFC_ADDR_OFFSET 0 #define SW_NDFC_ADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_CMD4_ADDR 0x0018 #define CFG_PAGE_RD_CMD_OFFSET 24 #define CFG_PAGE_RD_CMD_MASK 0xFF000000 #define CFG_PROG_EXE_CMD_OFFSET 16 #define CFG_PROG_EXE_CMD_MASK 0x00FF0000 //----------------------------------- #define CFG_NDFC_CMD5_ADDR 0x001c #define CFG_OIP_ADDR_OFFSET 0 #define CFG_OIP_ADDR_MASK 0x00FFFFFF //----------------------------------- #define CFG_NDFC_CFG0_ADDR 0x0030 #define NDFC_DATA_LE_OFFSET 16 #define NDFC_DATA_LE_MASK 0x00010000 #define NDFC_DUMMY_NUM_OFFSET 12 #define NDFC_DUMMY_NUM_MASK 0x00003000 #define SPI_1P8V_OFFSET 5 #define SPI_1P8V_MASK 0x00000020 #define NDFC_CRYPT_MODE_OFFSET 4 #define NDFC_CRYPT_MODE_MASK 0x00000010 //----------------------------------- #define CFG_NDFC_CLK0_ADDR 0x0034 #define CLK_SPI_NDFC_ENA_OFFSET 4 #define CLK_SPI_NDFC_ENA_MASK 0x00000010 #define CLK_SPI_NDFC_DIV_OFFSET 0 #define CLK_SPI_NDFC_DIV_MASK 0x00000007 //----------------------------------- #define CFG_NDFC_CFG1_ADDR 0x0040 #define CFG_PROG_WAIT_TIME_OFFSET 0 #define CFG_PROG_WAIT_TIME_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_CFG2_ADDR 0x00044 #define CFG_ERASE_WAIT_TIME_OFFSET 0 #define CFG_ERASE_WAIT_TIME_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_STS0_ADDR 0x0048 #define NDFC_CMD_FSM_STATE_OFFSET 12 #define NDFC_CMD_FSM_STATE_MASK 0x00007000 #define NDFC_CTRL_FSM_STATE_OFFSET 4 #define NDFC_CTRL_FSM_STATE_MASK 0x000001F0 #define NDFC_SPI_FSM_STATE_OFFSET 0 #define NDFC_SPI_FSM_STATE_MASK 0x00000007 //----------------------------------- #define CFG_NDFC_RDATA_ADDR 0x004c #define SW_NDFC_RDATA_OFFSET 0 #define SW_NDFC_RDATA_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_WDATA_ADDR 0x0050 #define SW_NDFC_WDATA_OFFSET 0 #define SW_NDFC_WDATA_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_DBG_ADDR 0x0054 #define NDFC_OIP_SEL_OFFSET 6 #define NDFC_OIP_SEL_MASK 0x000001C0 #define NDFC_SMC_IO_SHARE_OFFSET 5 #define NDFC_SMC_IO_SHARE_MASK 0x00000020 #define NDFC_TX_EDGE_SEL_OFFSET 4 #define NDFC_TX_EDGE_SEL_MASK 0x00000010 #define NDFC_ADDR_MAP_MODE_OFFSET 3 #define NDFC_ADDR_MAP_MODE_MASK 0x00000008 #define NDFC_ADDR_MAP_ENA_OFFSET 2 #define NDFC_ADDR_MAP_ENA_MASK 0x00000004 #define NDFC_RX_EDGE_SEL_OFFSET 1 #define NDFC_RX_EDGE_SEL_MASK 0x00000002 #define NDFC_CLK_FORCE_OUT_OFFSET 0 #define NDFC_CLK_FORCE_OUT_MASK 0x00000001 //----------------------------------- #define CFG_NDFC_AMAP0_ADDR 0x0060 #define NDFC_ABLK3_MAP_OFFSET 24 #define NDFC_ABLK3_MAP_MASK 0x1F000000 #define NDFC_ABLK2_MAP_OFFSET 16 #define NDFC_ABLK2_MAP_MASK 0x001F0000 #define NDFC_ABLK1_MAP_OFFSET 8 #define NDFC_ABLK1_MAP_MASK 0x00001F00 #define NDFC_ABLK0_MAP_OFFSET 0 #define NDFC_ABLK0_MAP_MASK 0x0000001F //----------------------------------- #define CFG_NDFC_AMAP1_ADDR 0x0064 #define NDFC_ABLK7_MAP_OFFSET 24 #define NDFC_ABLK7_MAP_MASK 0x1F000000 #define NDFC_ABLK6_MAP_OFFSET 16 #define NDFC_ABLK6_MAP_MASK 0x001F0000 #define NDFC_ABLK5_MAP_OFFSET 8 #define NDFC_ABLK5_MAP_MASK 0x00001F00 #define NDFC_ABLK4_MAP_OFFSET 0 #define NDFC_ABLK4_MAP_MASK 0x0000001F //----------------------------------- #define CFG_NDFC_AMAP2_ADDR 0x0068 #define NDFC_ABLK11_MAP_OFFSET 24 #define NDFC_ABLK11_MAP_MASK 0x1F000000 #define NDFC_ABLK10_MAP_OFFSET 16 #define NDFC_ABLK10_MAP_MASK 0x001F0000 #define NDFC_ABLK9_MAP_OFFSET 8 #define NDFC_ABLK9_MAP_MASK 0x00001F00 #define NDFC_ABLK8_MAP_OFFSET 0 #define NDFC_ABLK8_MAP_MASK 0x0000001F //----------------------------------- #define CFG_NDFC_AMAP3_ADDR 0x006c #define NDFC_ABLK15_MAP_OFFSET 24 #define NDFC_ABLK15_MAP_MASK 0x1F000000 #define NDFC_ABLK14_MAP_OFFSET 16 #define NDFC_ABLK14_MAP_MASK 0x001F0000 #define NDFC_ABLK13_MAP_OFFSET 8 #define NDFC_ABLK13_MAP_MASK 0x00001F00 #define NDFC_ABLK12_MAP_OFFSET 0 #define NDFC_ABLK12_MAP_MASK 0x0000001F //----------------------------------- #define CFG_NDFC_AMAP4_ADDR 0x0070 #define NDFC_ABLK19_MAP_OFFSET 24 #define NDFC_ABLK19_MAP_MASK 0x1F000000 #define NDFC_ABLK18_MAP_OFFSET 16 #define NDFC_ABLK18_MAP_MASK 0x001F0000 #define NDFC_ABLK17_MAP_OFFSET 8 #define NDFC_ABLK17_MAP_MASK 0x00001F00 #define NDFC_ABLK16_MAP_OFFSET 0 #define NDFC_ABLK16_MAP_MASK 0x0000001F //----------------------------------- #define CFG_NDFC_AMAP5_ADDR 0x0074 #define NDFC_ABLK23_MAP_OFFSET 24 #define NDFC_ABLK23_MAP_MASK 0x1F000000 #define NDFC_ABLK22_MAP_OFFSET 16 #define NDFC_ABLK22_MAP_MASK 0x001F0000 #define NDFC_ABLK21_MAP_OFFSET 8 #define NDFC_ABLK21_MAP_MASK 0x00001F00 #define NDFC_ABLK20_MAP_OFFSET 0 #define NDFC_ABLK20_MAP_MASK 0x0000001F //----------------------------------- #define CFG_NDFC_AMAP6_ADDR 0x0078 #define NDFC_ABLK27_MAP_OFFSET 24 #define NDFC_ABLK27_MAP_MASK 0x1F000000 #define NDFC_ABLK26_MAP_OFFSET 16 #define NDFC_ABLK26_MAP_MASK 0x001F0000 #define NDFC_ABLK25_MAP_OFFSET 8 #define NDFC_ABLK25_MAP_MASK 0x00001F00 #define NDFC_ABLK24_MAP_OFFSET 0 #define NDFC_ABLK24_MAP_MASK 0x0000001F //----------------------------------- #define CFG_NDFC_AMAP7_ADDR 0x007c #define NDFC_ABLK31_MAP_OFFSET 24 #define NDFC_ABLK31_MAP_MASK 0x1F000000 #define NDFC_ABLK30_MAP_OFFSET 16 #define NDFC_ABLK30_MAP_MASK 0x001F0000 #define NDFC_ABLK29_MAP_OFFSET 8 #define NDFC_ABLK29_MAP_MASK 0x00001F00 #define NDFC_ABLK28_MAP_OFFSET 0 #define NDFC_ABLK28_MAP_MASK 0x0000001F //----------------------------------- #define CFG_NDFC_SWM_CFG0_ADDR 0x0080 #define CFG_SPI_WR_OFFSET 9 #define CFG_SPI_WR_MASK 0x00000200 #define CFG_SPI_RD_OFFSET 8 #define CFG_SPI_RD_MASK 0x00000100 #define CFG_CMD_DUAL_MODE_OFFSET 7 #define CFG_CMD_DUAL_MODE_MASK 0x00000080 #define CFG_CMD_QUAD_MODE_OFFSET 6 #define CFG_CMD_QUAD_MODE_MASK 0x00000040 #define CFG_ADDR_DUAL_MODE_OFFSET 5 #define CFG_ADDR_DUAL_MODE_MASK 0x00000020 #define CFG_ADDR_QUAD_MODE_OFFSET 4 #define CFG_ADDR_QUAD_MODE_MASK 0x00000010 #define CFG_CMODE_DUAL_MODE_OFFSET 3 #define CFG_CMODE_DUAL_MODE_MASK 0x00000008 #define CFG_CMODE_QUAD_MODE_OFFSET 2 #define CFG_CMODE_QUAD_MODE_MASK 0x00000004 #define CFG_DATA_DUAL_MODE_OFFSET 1 #define CFG_DATA_DUAL_MODE_MASK 0x00000002 #define CFG_DATA_QUAD_MODE_OFFSET 0 #define CFG_DATA_QUAD_MODE_MASK 0x00000001 //----------------------------------- #define CFG_NDFC_SWM_CFG1_ADDR 0x0084 #define CFG_CMD_LEN_OFFSET 24 #define CFG_CMD_LEN_MASK 0x1F000000 #define CFG_ADDR_LEN_OFFSET 16 #define CFG_ADDR_LEN_MASK 0x001F0000 #define CFG_CMODE_LEN_OFFSET 8 #define CFG_CMODE_LEN_MASK 0x00001F00 #define CFG_DUMMY_LEN_OFFSET 0 #define CFG_DUMMY_LEN_MASK 0x0000001F //----------------------------------- #define CFG_NDFC_SWM_CFG2_ADDR 0x0088 #define CFG_CACHE_CMD_OFFSET 24 #define CFG_CACHE_CMD_MASK 0xFF000000 #define CFG_OIP_CMD_OFFSET 16 #define CFG_OIP_CMD_MASK 0x00FF0000 #define CFG_WR_EN_CMD_OFFSET 8 #define CFG_WR_EN_CMD_MASK 0x0000FF00 #define CFG_WR_DIS_CMD_OFFSET 0 #define CFG_WR_DIS_CMD_MASK 0x000000FF //----------------------------------- #define CFG_NDFC_CACHE_CFG0_ADDR 0x008c #define CACHE_SPI_WR_OFFSET 9 #define CACHE_SPI_WR_MASK 0x00000200 #define CACHE_SPI_RD_OFFSET 8 #define CACHE_SPI_RD_MASK 0x00000100 #define CACHE_CMD_DUAL_MODE_OFFSET 7 #define CACHE_CMD_DUAL_MODE_MASK 0x00000080 #define CACHE_CMD_QUAD_MODE_OFFSET 6 #define CACHE_CMD_QUAD_MODE_MASK 0x00000040 #define CACHE_ADDR_DUAL_MODE_OFFSET 5 #define CACHE_ADDR_DUAL_MODE_MASK 0x00000020 #define CACHE_ADDR_QUAD_MODE_OFFSET 4 #define CACHE_ADDR_QUAD_MODE_MASK 0x00000010 #define CACHE_CMODE_DUAL_MODE_OFFSET 3 #define CACHE_CMODE_DUAL_MODE_MASK 0x00000008 #define CACHE_CMODE_QUAD_MODE_OFFSET 2 #define CACHE_CMODE_QUAD_MODE_MASK 0x00000004 #define CACHE_DATA_DUAL_MODE_OFFSET 1 #define CACHE_DATA_DUAL_MODE_MASK 0x00000002 #define CACHE_DATA_QUAD_MODE_OFFSET 0 #define CACHE_DATA_QUAD_MODE_MASK 0x00000001 //----------------------------------- #define CFG_NDFC_CACHE_CFG1_ADDR 0x0090 #define CACHE_CMD_LEN_OFFSET 24 #define CACHE_CMD_LEN_MASK 0x1F000000 #define CACHE_ADDR_LEN_OFFSET 16 #define CACHE_ADDR_LEN_MASK 0x001F0000 #define CACHE_CMODE_LEN_OFFSET 8 #define CACHE_CMODE_LEN_MASK 0x00001F00 #define CACHE_DUMMY_LEN_OFFSET 0 #define CACHE_DUMMY_LEN_MASK 0x0000001F //----------------------------------- #define CFG_NDFC_OIP_CFG0_ADDR 0x0094 #define OIP_SPI_WR_OFFSET 9 #define OIP_SPI_WR_MASK 0x00000200 #define OIP_SPI_RD_OFFSET 8 #define OIP_SPI_RD_MASK 0x00000100 #define OIP_CMD_DUAL_MODE_OFFSET 7 #define OIP_CMD_DUAL_MODE_MASK 0x00000080 #define OIP_CMD_QUAD_MODE_OFFSET 6 #define OIP_CMD_QUAD_MODE_MASK 0x00000040 #define OIP_ADDR_DUAL_MODE_OFFSET 5 #define OIP_ADDR_DUAL_MODE_MASK 0x00000020 #define OIP_ADDR_QUAD_MODE_OFFSET 4 #define OIP_ADDR_QUAD_MODE_MASK 0x00000010 #define OIP_CMODE_DUAL_MODE_OFFSET 3 #define OIP_CMODE_DUAL_MODE_MASK 0x00000008 #define OIP_CMODE_QUAD_MODE_OFFSET 2 #define OIP_CMODE_QUAD_MODE_MASK 0x00000004 #define OIP_DATA_DUAL_MODE_OFFSET 1 #define OIP_DATA_DUAL_MODE_MASK 0x00000002 #define OIP_DATA_QUAD_MODE_OFFSET 0 #define OIP_DATA_QUAD_MODE_MASK 0x00000001 //----------------------------------- #define CFG_NDFC_WIP_CFG1_ADDR 0x0098 #define OIP_CMD_LEN_OFFSET 24 #define OIP_CMD_LEN_MASK 0x1F000000 #define OIP_ADDR_LEN_OFFSET 16 #define OIP_ADDR_LEN_MASK 0x001F0000 #define OIP_CMODE_LEN_OFFSET 8 #define OIP_CMODE_LEN_MASK 0x00001F00 #define OIP_DUMMY_LEN_OFFSET 0 #define OIP_DUMMY_LEN_MASK 0x0000001F //----------------------------------- #define CFG_NDFC_WR_EN_CFG0_ADDR 0x009c #define WR_EN_SPI_WR_OFFSET 9 #define WR_EN_SPI_WR_MASK 0x00000200 #define WR_EN_SPI_RD_OFFSET 8 #define WR_EN_SPI_RD_MASK 0x00000100 #define WR_EN_CMD_DUAL_MODE_OFFSET 7 #define WR_EN_CMD_DUAL_MODE_MASK 0x00000080 #define WR_EN_CMD_QUAD_MODE_OFFSET 6 #define WR_EN_CMD_QUAD_MODE_MASK 0x00000040 #define WR_EN_ADDR_DUAL_MODE_OFFSET 5 #define WR_EN_ADDR_DUAL_MODE_MASK 0x00000020 #define WR_EN_ADDR_QUAD_MODE_OFFSET 4 #define WR_EN_ADDR_QUAD_MODE_MASK 0x00000010 #define WR_EN_CMODE_DUAL_MODE_OFFSET 3 #define WR_EN_CMODE_DUAL_MODE_MASK 0x00000008 #define WR_EN_CMODE_QUAD_MODE_OFFSET 2 #define WR_EN_CMODE_QUAD_MODE_MASK 0x00000004 #define WR_EN_DATA_DUAL_MODE_OFFSET 1 #define WR_EN_DATA_DUAL_MODE_MASK 0x00000002 #define WR_EN_DATA_QUAD_MODE_OFFSET 0 #define WR_EN_DATA_QUAD_MODE_MASK 0x00000001 //----------------------------------- #define CFG_NDFC_WR_EN_CFG1_ADDR 0x00a0 #define WR_EN_CMD_LEN_OFFSET 24 #define WR_EN_CMD_LEN_MASK 0x1F000000 #define WR_EN_ADDR_LEN_OFFSET 16 #define WR_EN_ADDR_LEN_MASK 0x001F0000 #define WR_EN_CMODE_LEN_OFFSET 8 #define WR_EN_CMODE_LEN_MASK 0x00001F00 #define WR_EN_DUMMY_LEN_OFFSET 0 #define WR_EN_DUMMY_LEN_MASK 0x0000001F //----------------------------------- #define CFG_NDFC_WR_DIS_CFG0_ADDR 0x00a4 #define WR_DIS_SPI_WR_OFFSET 9 #define WR_DIS_SPI_WR_MASK 0x00000200 #define WR_DIS_SPI_RD_OFFSET 8 #define WR_DIS_SPI_RD_MASK 0x00000100 #define WR_DIS_CMD_DUAL_MODE_OFFSET 7 #define WR_DIS_CMD_DUAL_MODE_MASK 0x00000080 #define WR_DIS_CMD_QUAD_MODE_OFFSET 6 #define WR_DIS_CMD_QUAD_MODE_MASK 0x00000040 #define WR_DIS_ADDR_DUAL_MODE_OFFSET 5 #define WR_DIS_ADDR_DUAL_MODE_MASK 0x00000020 #define WR_DIS_ADDR_QUAD_MODE_OFFSET 4 #define WR_DIS_ADDR_QUAD_MODE_MASK 0x00000010 #define WR_DIS_CMODE_DUAL_MODE_OFFSET 3 #define WR_DIS_CMODE_DUAL_MODE_MASK 0x00000008 #define WR_DIS_CMODE_QUAD_MODE_OFFSET 2 #define WR_DIS_CMODE_QUAD_MODE_MASK 0x00000004 #define WR_DIS_DATA_DUAL_MODE_OFFSET 1 #define WR_DIS_DATA_DUAL_MODE_MASK 0x00000002 #define WR_DIS_DATA_QUAD_MODE_OFFSET 0 #define WR_DIS_DATA_QUAD_MODE_MASK 0x00000001 //----------------------------------- #define CFG_NDFC_WR_DIS_CFG1_ADDR 0x00a8 #define WR_DIS_CMD_LEN_OFFSET 24 #define WR_DIS_CMD_LEN_MASK 0x1F000000 #define WR_DIS_ADDR_LEN_OFFSET 16 #define WR_DIS_ADDR_LEN_MASK 0x001F0000 #define WR_DIS_CMODE_LEN_OFFSET 8 #define WR_DIS_CMODE_LEN_MASK 0x00001F00 #define WR_DIS_DUMMY_LEN_OFFSET 0 #define WR_DIS_DUMMY_LEN_MASK 0x0000001F //----------------------------------- #define CFG_NDFC_PAGE_RD_CFG0_ADDR 0x00ac #define PAGE_RD_SPI_WR_OFFSET 9 #define PAGE_RD_SPI_WR_MASK 0x00000200 #define PAGE_RD_SPI_RD_OFFSET 8 #define PAGE_RD_SPI_RD_MASK 0x00000100 #define PAGE_RD_CMD_DUAL_MODE_OFFSET 7 #define PAGE_RD_CMD_DUAL_MODE_MASK 0x00000080 #define PAGE_RD_CMD_QUAD_MODE_OFFSET 6 #define PAGE_RD_CMD_QUAD_MODE_MASK 0x00000040 #define PAGE_RD_ADDR_DUAL_MODE_OFFSET 5 #define PAGE_RD_ADDR_DUAL_MODE_MASK 0x00000020 #define PAGE_RD_ADDR_QUAD_MODE_OFFSET 4 #define PAGE_RD_ADDR_QUAD_MODE_MASK 0x00000010 #define PAGE_RD_CMODE_DUAL_MODE_OFFSET 3 #define PAGE_RD_CMODE_DUAL_MODE_MASK 0x00000008 #define PAGE_RD_CMODE_QUAD_MODE_OFFSET 2 #define PAGE_RD_CMODE_QUAD_MODE_MASK 0x00000004 #define PAGE_RD_DATA_DUAL_MODE_OFFSET 1 #define PAGE_RD_DATA_DUAL_MODE_MASK 0x00000002 #define PAGE_RD_DATA_QUAD_MODE_OFFSET 0 #define PAGE_RD_DATA_QUAD_MODE_MASK 0x00000001 //----------------------------------- #define CFG_NDFC_PAGE_RD_CFG1_ADDR 0x00b0 #define PAGE_RD_CMD_LEN_OFFSET 24 #define PAGE_RD_CMD_LEN_MASK 0x1F000000 #define PAGE_RD_ADDR_LEN_OFFSET 16 #define PAGE_RD_ADDR_LEN_MASK 0x001F0000 #define PAGE_RD_CMODE_LEN_OFFSET 8 #define PAGE_RD_CMODE_LEN_MASK 0x00001F00 #define PAGE_RD_DUMMY_LEN_OFFSET 0 #define PAGE_RD_DUMMY_LEN_MASK 0x0000001F //----------------------------------- #define CFG_NDFC_PAGE_EXE_CFG0_ADDR 0x00b4 #define PROG_EXE_SPI_WR_OFFSET 9 #define PROG_EXE_SPI_WR_MASK 0x00000200 #define PROG_EXE_SPI_RD_OFFSET 8 #define PROG_EXE_SPI_RD_MASK 0x00000100 #define PROG_EXE_CMD_DUAL_MODE_OFFSET 7 #define PROG_EXE_CMD_DUAL_MODE_MASK 0x00000080 #define PROG_EXE_CMD_QUAD_MODE_OFFSET 6 #define PROG_EXE_CMD_QUAD_MODE_MASK 0x00000040 #define PROG_EXE_ADDR_DUAL_MODE_OFFSET 5 #define PROG_EXE_ADDR_DUAL_MODE_MASK 0x00000020 #define PROG_EXE_ADDR_QUAD_MODE_OFFSET 4 #define PROG_EXE_ADDR_QUAD_MODE_MASK 0x00000010 #define PROG_EXE_CMODE_DUAL_MODE_OFFSET 3 #define PROG_EXE_CMODE_DUAL_MODE_MASK 0x00000008 #define PROG_EXE_CMODE_QUAD_MODE_OFFSET 2 #define PROG_EXE_CMODE_QUAD_MODE_MASK 0x00000004 #define PROG_EXE_DATA_DUAL_MODE_OFFSET 1 #define PROG_EXE_DATA_DUAL_MODE_MASK 0x00000002 #define PROG_EXE_DATA_QUAD_MODE_OFFSET 0 #define PROG_EXE_DATA_QUAD_MODE_MASK 0x00000001 //----------------------------------- #define CFG_NDFC_PAGE_EXE_CFG1_ADDR 0x00b8 #define PROG_EXE_CMD_LEN_OFFSET 24 #define PROG_EXE_CMD_LEN_MASK 0x1F000000 #define PROG_EXE_ADDR_LEN_OFFSET 16 #define PROG_EXE_ADDR_LEN_MASK 0x001F0000 #define PROG_EXE_CMODE_LEN_OFFSET 8 #define PROG_EXE_CMODE_LEN_MASK 0x00001F00 #define PROG_EXE_DUMMY_LEN_OFFSET 0 #define PROG_EXE_DUMMY_LEN_MASK 0x0000001F //----------------------------------- #define CFG_NDFC_DATA_RD_CFG0_ADDR 0x00bc #define DATA_RD_SPI_WR_OFFSET 9 #define DATA_RD_SPI_WR_MASK 0x00000200 #define DATA_RD_SPI_RD_OFFSET 8 #define DATA_RD_SPI_RD_MASK 0x00000100 #define DATA_RD_CMD_DUAL_MODE_OFFSET 7 #define DATA_RD_CMD_DUAL_MODE_MASK 0x00000080 #define DATA_RD_CMD_QUAD_MODE_OFFSET 6 #define DATA_RD_CMD_QUAD_MODE_MASK 0x00000040 #define DATA_RD_ADDR_DUAL_MODE_OFFSET 5 #define DATA_RD_ADDR_DUAL_MODE_MASK 0x00000020 #define DATA_RD_ADDR_QUAD_MODE_OFFSET 4 #define DATA_RD_ADDR_QUAD_MODE_MASK 0x00000010 #define DATA_RD_CMODE_DUAL_MODE_OFFSET 3 #define DATA_RD_CMODE_DUAL_MODE_MASK 0x00000008 #define DATA_RD_CMODE_QUAD_MODE_OFFSET 2 #define DATA_RD_CMODE_QUAD_MODE_MASK 0x00000004 #define DATA_RD_DATA_DUAL_MODE_OFFSET 1 #define DATA_RD_DATA_DUAL_MODE_MASK 0x00000002 #define DATA_RD_DATA_QUAD_MODE_OFFSET 0 #define DATA_RD_DATA_QUAD_MODE_MASK 0x00000001 //----------------------------------- #define CFG_NDFC_DATA_RD_CFG1_ADDR 0x00c0 #define DATA_RD_CMD_LEN_OFFSET 24 #define DATA_RD_CMD_LEN_MASK 0x1F000000 #define DATA_RD_ADDR_LEN_OFFSET 16 #define DATA_RD_ADDR_LEN_MASK 0x001F0000 #define DATA_RD_CMODE_LEN_OFFSET 8 #define DATA_RD_CMODE_LEN_MASK 0x00001F00 #define DATA_RD_DUMMY_LEN_OFFSET 0 #define DATA_RD_DUMMY_LEN_MASK 0x0000001F //----------------------------------- #define CFG_NDFC_PROG_LOAD_CFG0_ADDR 0x00c4 #define PROG_LOAD_SPI_WR_OFFSET 9 #define PROG_LOAD_SPI_WR_MASK 0x00000200 #define PROG_LOAD_SPI_RD_OFFSET 8 #define PROG_LOAD_SPI_RD_MASK 0x00000100 #define PROG_LOAD_CMD_DUAL_MODE_OFFSET 7 #define PROG_LOAD_CMD_DUAL_MODE_MASK 0x00000080 #define PROG_LOAD_CMD_QUAD_MODE_OFFSET 6 #define PROG_LOAD_CMD_QUAD_MODE_MASK 0x00000040 #define PROG_LOAD_ADDR_DUAL_MODE_OFFSET 5 #define PROG_LOAD_ADDR_DUAL_MODE_MASK 0x00000020 #define PROG_LOAD_ADDR_QUAD_MODE_OFFSET 4 #define PROG_LOAD_ADDR_QUAD_MODE_MASK 0x00000010 #define PROG_LOAD_CMODE_DUAL_MODE_OFFSET 3 #define PROG_LOAD_CMODE_DUAL_MODE_MASK 0x00000008 #define PROG_LOAD_CMODE_QUAD_MODE_OFFSET 2 #define PROG_LOAD_CMODE_QUAD_MODE_MASK 0x00000004 #define PROG_LOAD_DATA_DUAL_MODE_OFFSET 1 #define PROG_LOAD_DATA_DUAL_MODE_MASK 0x00000002 #define PROG_LOAD_DATA_QUAD_MODE_OFFSET 0 #define PROG_LOAD_DATA_QUAD_MODE_MASK 0x00000001 //----------------------------------- #define CFG_NDFC_PROG_LOAD_CFG1_ADDR 0x00c8 #define PROG_LOAD_CMD_LEN_OFFSET 24 #define PROG_LOAD_CMD_LEN_MASK 0x1F000000 #define PROG_LOAD_ADDR_LEN_OFFSET 16 #define PROG_LOAD_ADDR_LEN_MASK 0x001F0000 #define PROG_LOAD_CMODE_LEN_OFFSET 8 #define PROG_LOAD_CMODE_LEN_MASK 0x00001F00 #define PROG_LOAD_DUMMY_LEN_OFFSET 0 #define PROG_LOAD_DUMMY_LEN_MASK 0x0000001F //----------------------------------- #define CFG_NDFC_WAIT_TIME_ADDR 0x00cc #define CFG_PAGE_RD_WAIT_TIME_OFFSET 0 #define CFG_PAGE_RD_WAIT_TIME_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_DEBUG_ADDR 0x00d0 #define CFG_PAGE_RD_REUSE_OFFSET 14 #define CFG_PAGE_RD_REUSE_MASK 0x00004000 #define CFG_AHBM_IN_BYTE_ORDER_SEL_OFFSET 13 #define CFG_AHBM_IN_BYTE_ORDER_SEL_MASK 0x00002000 #define CFG_AHBM_IN_BIT_ORDER_SEL_OFFSET 12 #define CFG_AHBM_IN_BIT_ORDER_SEL_MASK 0x00001000 #define CFG_AHBM_OUT_BYTE_ORDER_SEL_OFFSET 11 #define CFG_AHBM_OUT_BYTE_ORDER_SEL_MASK 0x00000800 #define CFG_AHBM_OUT_BIT_ORDER_SEL_OFFSET 10 #define CFG_AHBM_OUT_BIT_ORDER_SEL_MASK 0x00000400 #define RO_NDFC_RX_OVERFLOW_OFFSET 9 #define RO_NDFC_RX_OVERFLOW_MASK 0x00000200 #define RO_NDFC_TX_UNDERFLOW_OFFSET 8 #define RO_NDFC_TX_UNDERFLOW_MASK 0x00000100 #define RO_NDFC_START_ADDR_EXCEED_PBSIZE_OFFSET 7 #define RO_NDFC_START_ADDR_EXCEED_PBSIZE_MASK 0x00000080 #define RO_NDFC_DATA_MODE_EXCEED_BOUNDARY_OFFSET 6 #define RO_NDFC_DATA_MODE_EXCEED_BOUNDARY_MASK 0x00000040 #define CFG_NDFC_RX_OVERFLOW_CLR_OFFSET 5 #define CFG_NDFC_RX_OVERFLOW_CLR_MASK 0x00000020 #define CFG_NDFC_TX_UNDERFLOW_CLR_OFFSET 4 #define CFG_NDFC_TX_UNDERFLOW_CLR_MASK 0x00000010 #define CFG_NDFC_START_ADDR_EXCEED_PBSIZE_CLR_OFFSET 3 #define CFG_NDFC_START_ADDR_EXCEED_PBSIZE_CLR_MASK 0x00000008 #define CFG_NDFC_DATA_MODE_EXCEED_BOUNDARY_CLR_OFFSET 2 #define CFG_NDFC_DATA_MODE_EXCEED_BOUNDARY_CLR_MASK 0x00000004 #define CFG_AHB_TRANS_DONE_SEL_OFFSET 1 #define CFG_AHB_TRANS_DONE_SEL_MASK 0x00000002 #define CFG_DMA_NEW_OFFSET 0 #define CFG_DMA_NEW_MASK 0x00000001 //----------------------------------- #define CFG_NDFC_RD_ADDR1_ADDR 0x00d4 #define SW_NDFC_ADDR1_OFFSET 0 #define SW_NDFC_ADDR1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_RD_ADDR2_ADDR 0x00d8 #define SW_NDFC_ADDR2_OFFSET 0 #define SW_NDFC_ADDR2_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_RD_ADDR3_ADDR 0x00dc #define SW_NDFC_ADDR3_OFFSET 0 #define SW_NDFC_ADDR3_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_RD_ADDR4_ADDR 0x00e0 #define SW_NDFC_ADDR4_OFFSET 0 #define SW_NDFC_ADDR4_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_RD_ADDR5_ADDR 0x00e4 #define SW_NDFC_ADDR5_OFFSET 0 #define SW_NDFC_ADDR5_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_RD_ADDR6_ADDR 0x00e8 #define SW_NDFC_ADDR6_OFFSET 0 #define SW_NDFC_ADDR6_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_RD_ADDR7_ADDR 0x00ec #define SW_NDFC_ADDR7_OFFSET 0 #define SW_NDFC_ADDR7_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_RD_DMA_ADDR1_ADDR 0x00f0 #define SW_DMA_START_ADDR1_OFFSET 0 #define SW_DMA_START_ADDR1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_RD_DMA_ADDR2_ADDR 0x00f4 #define SW_DMA_START_ADDR2_OFFSET 0 #define SW_DMA_START_ADDR2_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_RD_DMA_ADDR3_ADDR 0x00f8 #define SW_DMA_START_ADDR3_OFFSET 0 #define SW_DMA_START_ADDR3_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_RD_DMA_ADDR4_ADDR 0x00fc #define SW_DMA_START_ADDR4_OFFSET 0 #define SW_DMA_START_ADDR4_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_RD_DMA_ADDR5_ADDR 0x0100 #define SW_DMA_START_ADDR5_OFFSET 0 #define SW_DMA_START_ADDR5_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_RD_DMA_ADDR6_ADDR 0x0104 #define SW_DMA_START_ADDR6_OFFSET 0 #define SW_DMA_START_ADDR6_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_RD_DMA_ADDR7_ADDR 0x0108 #define SW_DMA_START_ADDR7_OFFSET 0 #define SW_DMA_START_ADDR7_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NDFC_RD_DLEN1_ADDR 0x010c #define SW_NDFC_DLEN1_OFFSET 12 #define SW_NDFC_DLEN1_MASK 0x00FFF000 #define SW_NDFC_DLEN2_OFFSET 0 #define SW_NDFC_DLEN2_MASK 0x00000FFF //----------------------------------- #define CFG_NDFC_RD_DLEN2_ADDR 0x0110 #define SW_NDFC_DLEN3_OFFSET 12 #define SW_NDFC_DLEN3_MASK 0x00FFF000 #define SW_NDFC_DLEN4_OFFSET 0 #define SW_NDFC_DLEN4_MASK 0x00000FFF //----------------------------------- #define CFG_NDFC_RD_DLEN3_ADDR 0x0114 #define SW_NDFC_DLEN5_OFFSET 12 #define SW_NDFC_DLEN5_MASK 0x00FFF000 #define SW_NDFC_DLEN6_OFFSET 0 #define SW_NDFC_DLEN6_MASK 0x00000FFF //----------------------------------- #define CFG_NDFC_RD_DLEN4_ADDR 0x0118 #define SW_NDFC_DLEN7_OFFSET 0 #define SW_NDFC_DLEN7_MASK 0x00000FFF //----------------------------------- #define CFG_NDFC_ERASE_CFG1_ADDR 0x011c #define ERASE_CMD_LEN_OFFSET 24 #define ERASE_CMD_LEN_MASK 0x1F000000 #define ERASE_ADDR_LEN_OFFSET 16 #define ERASE_ADDR_LEN_MASK 0x001F0000 #define ERASE_CMODE_LEN_OFFSET 8 #define ERASE_CMODE_LEN_MASK 0x00001F00 #define ERASE_DUMMY_LEN_OFFSET 0 #define ERASE_DUMMY_LEN_MASK 0x0000001F //----------------------------------- #define CFG_NDFC_INTERRUPT_ADDR 0x0120 #define NDFC_INT_STATUS_OFFSET 14 #define NDFC_INT_STATUS_MASK 0x001FC000 #define CFG_NDFC_INT_MASK_OFFSET 7 #define CFG_NDFC_INT_MASK_MASK 0x00003F80 #define CFG_NDFC_INT_CLR_6_OFFSET 6 #define CFG_NDFC_INT_CLR_6_MASK 0x00000040 #define CFG_NDFC_INT_CLR_5_OFFSET 5 #define CFG_NDFC_INT_CLR_5_MASK 0x00000020 #define CFG_NDFC_INT_CLR_4_OFFSET 4 #define CFG_NDFC_INT_CLR_4_MASK 0x00000010 #define CFG_NDFC_INT_CLR_3_OFFSET 3 #define CFG_NDFC_INT_CLR_3_MASK 0x00000008 #define CFG_NDFC_INT_CLR_2_OFFSET 2 #define CFG_NDFC_INT_CLR_2_MASK 0x00000004 #define CFG_NDFC_INT_CLR_1_OFFSET 1 #define CFG_NDFC_INT_CLR_1_MASK 0x00000002 #define CFG_NDFC_INT_CLR_0_OFFSET 0 #define CFG_NDFC_INT_CLR_0_MASK 0x00000001 //HW module read/write macro #define NDFC_RF_READ_REG(addr) SOC_READ_REG(NDFC_RF_BASEADDR + addr) #define NDFC_RF_WRITE_REG(addr,value) SOC_WRITE_REG(NDFC_RF_BASEADDR + addr,value)