//-----------------------------------
#define CFG_EIG_EIG_CTRL0_ADDR 0x000
#define EIG_NUM_OPERATION_OFFSET 16
#define EIG_NUM_OPERATION_MASK 0xFFFF0000
#define EIG_TERM_CTRL_OFFSET 12
#define EIG_TERM_CTRL_MASK 0x0000F000
#define EIG_FORCE_ON_OFFSET 11
#define EIG_FORCE_ON_MASK 0x00000800
#define EIG_FP_RND_OFFSET 8
#define EIG_FP_RND_MASK 0x00000700
#define EIG_NUM_ITERATION_OFFSET 3
#define EIG_NUM_ITERATION_MASK 0x000000F8
#define EIG_MATRIX_SIZE_OFFSET 0
#define EIG_MATRIX_SIZE_MASK 0x00000007

//-----------------------------------
#define CFG_EIG_EIG_CTRL1_ADDR 0x004
#define EIG_SRC_START_ADDRESS_OFFSET 0
#define EIG_SRC_START_ADDRESS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EIG_EIG_CTRL2_ADDR 0x008
#define EIG_SRC_SIZE_OFFSET 0
#define EIG_SRC_SIZE_MASK 0x000000FF

//-----------------------------------
#define CFG_EIG_EIG_CTRL3_ADDR 0x00C
#define EIG_EIG_START_ADDRESS_OFFSET 0
#define EIG_EIG_START_ADDRESS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EIG_EIG_CTRL4_ADDR 0x010
#define EIG_VEC_START_ADDRESS_OFFSET 0
#define EIG_VEC_START_ADDRESS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EIG_EIG_CTRL5_ADDR 0x014
#define EIG_NORM_START_ADDRESS_OFFSET 0
#define EIG_NORM_START_ADDRESS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EIG_EIG_START_ADDR 0x018
#define EIG_EIG_START_TRIG_OFFSET 0
#define EIG_EIG_START_TRIG_MASK 0x00000001

//-----------------------------------
#define CFG_EIG_EIG_STATUS_ADDR 0x01C
#define EIG_EIG_DONE_OFFSET 31
#define EIG_EIG_DONE_MASK 0x80000000
#define EIG_FP_OP_STATUS_OFFSET 16
#define EIG_FP_OP_STATUS_MASK 0x00FF0000
#define EIG_EIG_COMPLETE_COUNT_OFFSET 0
#define EIG_EIG_COMPLETE_COUNT_MASK 0x0000FFFF

//-----------------------------------
#define CFG_EIG_EIG_INT_CLR_ADDR 0x020
#define EIG_EIG_INT_CLR_OFFSET 0
#define EIG_EIG_INT_CLR_MASK 0x00000001

//HW module read/write macro
#define RGF_EIG0_READ_REG(addr) SOC_READ_REG(RGF_EIG0_BASEADDR + addr)
#define RGF_EIG0_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_EIG0_BASEADDR + addr,value)
#define RGF_EIG1_READ_REG(addr) SOC_READ_REG(RGF_EIG1_BASEADDR + addr)
#define RGF_EIG1_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_EIG1_BASEADDR + addr,value)