//-----------------------------------
#define CFG_SMC_RVER_ADDR 0x0000
#define SMC_RF_VER_OFFSET 0
#define SMC_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SMC_CMD0_ADDR 0x0004
#define SW_SMC_ENA_OFFSET 31
#define SW_SMC_ENA_MASK 0x80000000
#define SW_SMC_DLEN_OFFSET 16
#define SW_SMC_DLEN_MASK 0x01FF0000
#define SW_SMC_CMODE_OFFSET 8
#define SW_SMC_CMODE_MASK 0x0000FF00
#define SW_SMC_MODE_OFFSET 0
#define SW_SMC_MODE_MASK 0x00000003

//-----------------------------------
#define CFG_SMC_CMD1_ADDR 0x0008
#define SW_SMC_CMD_OFFSET 24
#define SW_SMC_CMD_MASK 0xFF000000
#define SW_SMC_ADDR_OFFSET 0
#define SW_SMC_ADDR_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_SMC_CFG0_ADDR 0x000c
#define SOFT_SMC_MODE_OFFSET 25
#define SOFT_SMC_MODE_MASK 0x02000000
#define SMC_DATA_LE_OFFSET 24
#define SMC_DATA_LE_MASK 0x01000000
#define SMC_DUMMY_NUM_OFFSET 20
#define SMC_DUMMY_NUM_MASK 0x00300000
#define SMC_CLK_SPI_DIV2_OFFSET 16
#define SMC_CLK_SPI_DIV2_MASK 0x00010000
#define SMC_SPI_QPI_MODE_OFFSET 12
#define SMC_SPI_QPI_MODE_MASK 0x00001000
#define SMC_CACHE_WR_MODE_OFFSET 8
#define SMC_CACHE_WR_MODE_MASK 0x00000700
#define SMC_CRYPT_MODE_OFFSET 4
#define SMC_CRYPT_MODE_MASK 0x00000010
#define SMC_CACHE_RD_MODE_OFFSET 0
#define SMC_CACHE_RD_MODE_MASK 0x00000007

//-----------------------------------
#define CFG_SMC_CLK0_ADDR 0x0010
#define CLK_SPI_SMC_FORCE_DIV_OFFSET 5
#define CLK_SPI_SMC_FORCE_DIV_MASK 0x00000020
#define CLK_SPI_SMC_ENA_OFFSET 4
#define CLK_SPI_SMC_ENA_MASK 0x00000010
#define CLK_SPI_SMC_DIV_OFFSET 0
#define CLK_SPI_SMC_DIV_MASK 0x00000007

//-----------------------------------
#define CFG_SMC_STS0_ADDR 0x0018
#define SMC_FSM_STATE_OFFSET 4
#define SMC_FSM_STATE_MASK 0x000001F0
#define SPI_FSM_STATE_OFFSET 0
#define SPI_FSM_STATE_MASK 0x00000007

//-----------------------------------
#define CFG_SMC_RDATA_ADDR 0x001c
#define SW_SMC_RDATA_OFFSET 0
#define SW_SMC_RDATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SMC_WDATA_ADDR 0x0020
#define SW_SMC_WDATA_OFFSET 0
#define SW_SMC_WDATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SMC_DBG0_ADDR 0x0024
#define SMC_CLK_FORCE_OUT_OFFSET 2
#define SMC_CLK_FORCE_OUT_MASK 0x00000004
#define SMC_TX_EDGE_SEL_OFFSET 1
#define SMC_TX_EDGE_SEL_MASK 0x00000002
#define SMC_RX_EDGE_SEL_OFFSET 0
#define SMC_RX_EDGE_SEL_MASK 0x00000001

//-----------------------------------
#define CFG_SMC_SWM_CFG0_ADDR 0x0028
#define SMC_CFG_SPI_WR_OFFSET 9
#define SMC_CFG_SPI_WR_MASK 0x00000200
#define SMC_CFG_SPI_RD_OFFSET 8
#define SMC_CFG_SPI_RD_MASK 0x00000100
#define SMC_CFG_CMD_DUAL_MODE_OFFSET 7
#define SMC_CFG_CMD_DUAL_MODE_MASK 0x00000080
#define SMC_CFG_CMD_QUAD_MODE_OFFSET 6
#define SMC_CFG_CMD_QUAD_MODE_MASK 0x00000040
#define SMC_CFG_ADDR_DUAL_MODE_OFFSET 5
#define SMC_CFG_ADDR_DUAL_MODE_MASK 0x00000020
#define SMC_CFG_ADDR_QUAD_MODE_OFFSET 4
#define SMC_CFG_ADDR_QUAD_MODE_MASK 0x00000010
#define SMC_CFG_DATA_DUAL_MODE_OFFSET 1
#define SMC_CFG_DATA_DUAL_MODE_MASK 0x00000002
#define SMC_CFG_DATA_QUAD_MODE_OFFSET 0
#define SMC_CFG_DATA_QUAD_MODE_MASK 0x00000001

//-----------------------------------
#define CFG_SMC_SWM_CFG1_ADDR 0x002c
#define SMC_CFG_CMD_LEN_OFFSET 24
#define SMC_CFG_CMD_LEN_MASK 0x1F000000
#define SMC_CFG_ADDR_LEN_OFFSET 16
#define SMC_CFG_ADDR_LEN_MASK 0x001F0000
#define SMC_CFG_CMODE_LEN_OFFSET 8
#define SMC_CFG_CMODE_LEN_MASK 0x00001F00
#define SMC_CFG_DUMMY_LEN_OFFSET 0
#define SMC_CFG_DUMMY_LEN_MASK 0x0000001F

//-----------------------------------
#define CFG_SMC_CACHE_CFG_ADDR 0x0030
#define SMC_CACHE_RD_CMD_OFFSET 24
#define SMC_CACHE_RD_CMD_MASK 0xFF000000
#define SMC_CACHE_WR_CMD_OFFSET 16
#define SMC_CACHE_WR_CMD_MASK 0x00FF0000

//-----------------------------------
#define CFG_SMC_CACHE_RCFG0_ADDR 0x0034
#define CACHE_RD_CMD_DUAL_MODE_OFFSET 7
#define CACHE_RD_CMD_DUAL_MODE_MASK 0x00000080
#define CACHE_RD_CMD_QUAD_MODE_OFFSET 6
#define CACHE_RD_CMD_QUAD_MODE_MASK 0x00000040
#define CACHE_RD_ADDR_DUAL_MODE_OFFSET 5
#define CACHE_RD_ADDR_DUAL_MODE_MASK 0x00000020
#define CACHE_RD_ADDR_QUAD_MODE_OFFSET 4
#define CACHE_RD_ADDR_QUAD_MODE_MASK 0x00000010
#define CACHE_RD_DATA_DUAL_MODE_OFFSET 1
#define CACHE_RD_DATA_DUAL_MODE_MASK 0x00000002
#define CACHE_RD_DATA_QUAD_MODE_OFFSET 0
#define CACHE_RD_DATA_QUAD_MODE_MASK 0x00000001

//-----------------------------------
#define CFG_SMC_CACHE_RCFG1_ADDR 0x0038
#define CACHE_RD_CMD_LEN_OFFSET 24
#define CACHE_RD_CMD_LEN_MASK 0x1F000000
#define CACHE_RD_ADDR_LEN_OFFSET 16
#define CACHE_RD_ADDR_LEN_MASK 0x001F0000
#define CACHE_RD_DUMMY_LEN_OFFSET 0
#define CACHE_RD_DUMMY_LEN_MASK 0x0000001F

//-----------------------------------
#define CFG_SMC_CACHE_WCFG0_ADDR 0x003c
#define CACHE_WR_CMD_DUAL_MODE_OFFSET 7
#define CACHE_WR_CMD_DUAL_MODE_MASK 0x00000080
#define CACHE_WR_CMD_QUAD_MODE_OFFSET 6
#define CACHE_WR_CMD_QUAD_MODE_MASK 0x00000040
#define CACHE_WR_ADDR_DUAL_MODE_OFFSET 5
#define CACHE_WR_ADDR_DUAL_MODE_MASK 0x00000020
#define CACHE_WR_ADDR_QUAD_MODE_OFFSET 4
#define CACHE_WR_ADDR_QUAD_MODE_MASK 0x00000010
#define CACHE_WR_DATA_DUAL_MODE_OFFSET 1
#define CACHE_WR_DATA_DUAL_MODE_MASK 0x00000002
#define CACHE_WR_DATA_QUAD_MODE_OFFSET 0
#define CACHE_WR_DATA_QUAD_MODE_MASK 0x00000001

//-----------------------------------
#define CFG_SMC_CACHE_WCFG1_ADDR 0x0040
#define CACHE_WR_CMD_LEN_OFFSET 24
#define CACHE_WR_CMD_LEN_MASK 0x1F000000
#define CACHE_WR_ADDR_LEN_OFFSET 16
#define CACHE_WR_ADDR_LEN_MASK 0x001F0000
#define CACHE_WR_DUMMY_LEN_OFFSET 0
#define CACHE_WR_DUMMY_LEN_MASK 0x0000001F

//HW module read/write macro
#define SMC_RF_READ_REG(addr) SOC_READ_REG(SMC_RF_BASEADDR + addr)
#define SMC_RF_WRITE_REG(addr,value) SOC_WRITE_REG(SMC_RF_BASEADDR + addr,value)