//-----------------------------------
#define CFG_CTRLR0_ADDR 0x006c
#define TMOD_OFFSET 14
#define TMOD_MASK 0x0000C000
#define SLV_OE_OFFSET 13
#define SLV_OE_MASK 0x00002000
#define SRL_OFFSET 12
#define SRL_MASK 0x00001000
#define CFS_OFFSET 8
#define CFS_MASK 0x00000F00
#define DFS_OFFSET 4
#define DFS_MASK 0x000000F0
#define FRF_OFFSET 2
#define FRF_MASK 0x0000000C
#define SCPH_OFFSET 1
#define SCPH_MASK 0x00000002
#define SCPOL_OFFSET 0
#define SCPOL_MASK 0x00000001

//-----------------------------------
#define CFG_CTRLR1_ADDR 0x0068
#define NDF_OFFSET 0
#define NDF_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SSIENR_ADDR 0x0064
#define HW_TX_EB_OFFSET 2
#define HW_TX_EB_MASK 0x00000004
#define HW_RX_EB_OFFSET 1
#define HW_RX_EB_MASK 0x00000002
#define SSI_EN_OFFSET 0
#define SSI_EN_MASK 0x00000001

//-----------------------------------
#define CFG_MWCR_ADDR 0x0060
#define MHS_OFFSET 2
#define MHS_MASK 0x00000004
#define MDD_OFFSET 1
#define MDD_MASK 0x00000002
#define MWMOD_OFFSET 0
#define MWMOD_MASK 0x00000001

//-----------------------------------
#define CFG_SER_ADDR 0x005c
#define SER_OFFSET 0
#define SER_MASK 0x00000001

//-----------------------------------
#define CFG_BAUDR_ADDR 0x0058
#define SCKDV_OFFSET 0
#define SCKDV_MASK 0x0000FFFF

//-----------------------------------
#define CFG_TXFTLR_ADDR 0x0054
#define TFT_OFFSET 0
#define TFT_MASK 0x0000000F

//-----------------------------------
#define CFG_RXFTLR_ADDR 0x0050
#define RFT_OFFSET 0
#define RFT_MASK 0x0000000F

//-----------------------------------
#define CFG_TXFLR_ADDR 0x004C
#define TFFLR_OFFSET 0
#define TFFLR_MASK 0x0000000F

//-----------------------------------
#define CFG_RXFLR_ADDR 0x0048
#define RFFLR_OFFSET 0
#define RFFLR_MASK 0x0000000F

//-----------------------------------
#define CFG_SR_ADDR 0x0044
#define DCOL_OFFSET 6
#define DCOL_MASK 0x00000040
#define TXE_OFFSET 5
#define TXE_MASK 0x00000020
#define RFF_OFFSET 4
#define RFF_MASK 0x00000010
#define RFNE_OFFSET 3
#define RFNE_MASK 0x00000008
#define TFE_OFFSET 2
#define TFE_MASK 0x00000004
#define TFNF_OFFSET 1
#define TFNF_MASK 0x00000002
#define BUSY_OFFSET 0
#define BUSY_MASK 0x00000001

//-----------------------------------
#define CFG_IMR_ADDR 0x0040
#define MSTIM_OFFSET 5
#define MSTIM_MASK 0x00000020
#define RXFIM_OFFSET 4
#define RXFIM_MASK 0x00000010
#define RXOIM_OFFSET 3
#define RXOIM_MASK 0x00000008
#define RXUIM_OFFSET 2
#define RXUIM_MASK 0x00000004
#define TXOIM_OFFSET 1
#define TXOIM_MASK 0x00000002
#define TXEIM_OFFSET 0
#define TXEIM_MASK 0x00000001

//-----------------------------------
#define CFG_ISR_ADDR 0x003c
#define MSTIS_OFFSET 5
#define MSTIS_MASK 0x00000020
#define RXFIS_OFFSET 4
#define RXFIS_MASK 0x00000010
#define RXOIS_OFFSET 3
#define RXOIS_MASK 0x00000008
#define RXUIS_OFFSET 2
#define RXUIS_MASK 0x00000004
#define TXOIS_OFFSET 1
#define TXOIS_MASK 0x00000002
#define TXEIS_OFFSET 0
#define TXEIS_MASK 0x00000001

//-----------------------------------
#define CFG_RISR_ADDR 0x0038
#define MSTIR_OFFSET 5
#define MSTIR_MASK 0x00000020
#define RXFIR_OFFSET 4
#define RXFIR_MASK 0x00000010
#define RXOIR_OFFSET 3
#define RXOIR_MASK 0x00000008
#define RXUIR_OFFSET 2
#define RXUIR_MASK 0x00000004
#define TXOIR_OFFSET 1
#define TXOIR_MASK 0x00000002
#define TXEIR_OFFSET 0
#define TXEIR_MASK 0x00000001

//-----------------------------------
#define CFG_TXOICR_ADDR 0x0034
#define TXOCIR_OFFSET 0
#define TXOCIR_MASK 0x00000001

//-----------------------------------
#define CFG_RXOICR_ADDR 0x0030
#define RXOCIR_OFFSET 0
#define RXOCIR_MASK 0x00000001

//-----------------------------------
#define CFG_RXUICR_ADDR 0x002c
#define RXUCIR_OFFSET 0
#define RXUCIR_MASK 0x00000001

//-----------------------------------
#define CFG_MXTICR_ADDR 0x0028
#define MSTCIR_OFFSET 0
#define MSTCIR_MASK 0x00000001

//-----------------------------------
#define CFG_ICR_ADDR 0x0024
#define ICR_OFFSET 0
#define ICR_MASK 0x00000001

//-----------------------------------
#define CFG_DMACR_ADDR 0x0020
#define TDMAE_OFFSET 1
#define TDMAE_MASK 0x00000002
#define RDMAE_OFFSET 0
#define RDMAE_MASK 0x00000001

//-----------------------------------
#define CFG_DMATDLR_ADDR 0x001C
#define DMATDL_OFFSET 0
#define DMATDL_MASK 0x0000000F

//-----------------------------------
#define CFG_DMARDLR_ADDR 0x0018
#define DMARDL_OFFSET 0
#define DMARDL_MASK 0x0000000F

//-----------------------------------
#define CFG_IDR_ADDR 0x0014

//-----------------------------------
#define CFG_SSI_VERSION_ID_ADDR 0x0010

//-----------------------------------
#define CFG_RX_SAMPLE_DLY_ADDR 0x000c
#define RSD_OFFSET 0
#define RSD_MASK 0x000000FF

//-----------------------------------
#define CFG_SPI_CTRLR0_ADDR 0x0008
#define RSVD_SPI_CTRLR0_OFFSET 19
#define RSVD_SPI_CTRLR0_MASK 0xFFF80000
#define SPI_RXDS_EN_OFFSET 18
#define SPI_RXDS_EN_MASK 0x00040000
#define INST_DDR_EN_OFFSET 17
#define INST_DDR_EN_MASK 0x00020000
#define SPI_DDR_EN_OFFSET 16
#define SPI_DDR_EN_MASK 0x00010000
#define WAIT_CYCLES_OFFSET 11
#define WAIT_CYCLES_MASK 0x0000F800
#define RSVD_SPI_CTRLR0_10_OFFSET 10
#define RSVD_SPI_CTRLR0_10_MASK 0x00000400
#define INST_L_OFFSET 8
#define INST_L_MASK 0x00000300
#define RSVD_SPI_CTRLR0_6_7_OFFSET 6
#define RSVD_SPI_CTRLR0_6_7_MASK 0x000000C0
#define ADDR_L_OFFSET 2
#define ADDR_L_MASK 0x0000003C
#define TRANS_TYPE_OFFSET 0
#define TRANS_TYPE_MASK 0x00000003

//-----------------------------------
#define CFG_TXD_DRIVE_EDGE_ADDR 0x0004
#define TDE_OFFSET 0
#define TDE_MASK 0x000000FF

//-----------------------------------
#define CFG_RSVD_ADDR 0x0000

//-----------------------------------
#define CFG_DR0_ADDR 0x0070
#define DR0_OFFSET 0
#define DR0_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR1_ADDR 0x0074
#define DR1_OFFSET 0
#define DR1_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR2_ADDR 0x0078
#define DR2_OFFSET 0
#define DR2_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR3_ADDR 0x007c
#define DR3_OFFSET 0
#define DR3_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR4_ADDR 0x0080
#define DR4_OFFSET 0
#define DR4_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR5_ADDR 0x0084
#define DR5_OFFSET 0
#define DR5_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR6_ADDR 0x0088
#define DR6_OFFSET 0
#define DR6_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR7_ADDR 0x008c
#define DR7_OFFSET 0
#define DR7_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR8_ADDR 0x0090
#define DR8_OFFSET 0
#define DR8_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR9_ADDR 0x0094
#define DR9_OFFSET 0
#define DR9_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR10_ADDR 0x0098
#define DR10_OFFSET 0
#define DR10_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR11_ADDR 0x009c
#define DR11_OFFSET 0
#define DR11_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR12_ADDR 0x00a0
#define DR12_OFFSET 0
#define DR12_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR13_ADDR 0x00a4
#define DR13_OFFSET 0
#define DR13_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR14_ADDR 0x00a8
#define DR14_OFFSET 0
#define DR14_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR15_ADDR 0x00ac
#define DR15_OFFSET 0
#define DR15_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR16_ADDR 0x00b0
#define DR16_OFFSET 0
#define DR16_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR17_ADDR 0x00b4
#define DR17_OFFSET 0
#define DR17_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR18_ADDR 0x00b8
#define DR18_OFFSET 0
#define DR18_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR19_ADDR 0x00bc
#define DR19_OFFSET 0
#define DR19_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR20_ADDR 0x00c0
#define DR20_OFFSET 0
#define DR20_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR21_ADDR 0x00c4
#define DR21_OFFSET 0
#define DR21_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR22_ADDR 0x00c8
#define DR22_OFFSET 0
#define DR22_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR23_ADDR 0x00cc
#define DR23_OFFSET 0
#define DR23_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR24_ADDR 0x00d0
#define DR24_OFFSET 0
#define DR24_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR25_ADDR 0x00d4
#define DR25_OFFSET 0
#define DR25_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR26_ADDR 0x00d8
#define DR26_OFFSET 0
#define DR26_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR27_ADDR 0x00dc
#define DR27_OFFSET 0
#define DR27_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR28_ADDR 0x00e0
#define DR28_OFFSET 0
#define DR28_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR29_ADDR 0x00e4
#define DR29_OFFSET 0
#define DR29_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR30_ADDR 0x00e8
#define DR30_OFFSET 0
#define DR30_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR31_ADDR 0x00ec
#define DR31_OFFSET 0
#define DR31_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR32_ADDR 0x00f0
#define DR32_OFFSET 0
#define DR32_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR33_ADDR 0x00f4
#define DR33_OFFSET 0
#define DR33_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR34_ADDR 0x00f8
#define DR34_OFFSET 0
#define DR34_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DR35_ADDR 0x00fc
#define DR35_OFFSET 0
#define DR35_MASK 0x0000FFFF

//HW module read/write macro
#define SPI_READ_REG(addr) SOC_READ_REG(SPI_BASEADDR + addr)
#define SPI_WRITE_REG(addr,value) SOC_WRITE_REG(SPI_BASEADDR + addr,value)
#define SPI1_READ_REG(addr) SOC_READ_REG(SPI1_BASEADDR + addr)
#define SPI1_WRITE_REG(addr,value) SOC_WRITE_REG(SPI1_BASEADDR + addr,value)
#define SPI2_READ_REG(addr) SOC_READ_REG(SPI2_BASEADDR + addr)
#define SPI2_WRITE_REG(addr,value) SOC_WRITE_REG(SPI2_BASEADDR + addr,value)