#define UART0_BASEADDR 			0x44001000
#define UART1_BASEADDR 			0x44005000
#define UART2_BASEADDR 			0x44006000

/* CR bits */
#define CTSEN  (1<<15)
#define RTSEN  (1<<14)
#define OUT2   (1<<13)
#define OUT1   (1<<12)
#define RTS    (1<<11)
#define DTR    (1<<10)
#define RXE    (1<<9) /* Receive enable */
#define TXE    (1<<8) /* Transmit enable */
#define LPE    (1<<7)
#define IIRLP  (1<<2)
#define SIREN  (1<<1)
#define UARTEN (1<<0) /* UART enable */

/* FR bits */
#define TXFE   (1<<7) /* TX FIFO empty */
#define RXFF   (1<<6)
#define TXFF   (1<<5)
#define RXFE   (1<<4) /* RX FIFO empty */
#define BUSY   (1<<3)
#define TMSK    TXFF|BUSY

/* LCR_H bits */
#define SPS    (1<<7) /* Stick parity select */
#define WLEN_8 (3<<5)
#define WLEN_7 (2<<5)
#define WLEN_6 (1<<5)
#define WLEN_5 (0<<5)
#define FEN    (1<<4) /* FIFO enable */
#define STP2   (1<<3) /* Two stop bits select */
#define EPS    (1<<2) /* Even parity select */
#define PEN    (1<<1) /* Parity enable */
#define BRK    (1<<0) /* Send break */

/* Interrupt bits (IMSC, MIS, ICR) */
#define OEI   (1<<10) /* Overrun Error interrupt mask */
#define BEI   (1<<9)  /* Break Error interrupt mask */
#define PEI   (1<<8)  /* Parity Error interrupt mask */
#define FEI   (1<<7)  /* Framing Error interrupt mask */
#define RTI   (1<<6)  /* Receive Timeout interrupt mask */
#define TXI   (1<<5)  /* Transmit interrupt mask */
#define RXI   (1<<4)  /* Receive interrupt mask */
#define DSRMI (1<<3)  /* nUARTDSR Modem interrupt mask */
#define DCDMI (1<<2)  /* nUARTDCD Modem interrupt mask */
#define CTSMI (1<<1)  /* nUARTCTS Modem interrupt mask */
#define RIMI  (1<<0)  /* nUARTRI Modem interrupt mask */
#define ALLI  OEI|BEI|PEI|FEI|RTI|TXI|RXI|DSRMI|DCDMI|CTSMI|RIMI

/* These parity settings can be ORed directly into the LCR. */
#define PARITY_NONE  (0)
#define PARITY_ODD   (PEN)
#define PARITY_EVEN  (PEN|EPS)
#define PARITY_MARK  (PEN|SPS)
#define PARITY_SPACE (PEN|EPS|SPS)