//-----------------------------------
#define CFG_ADA_BASIC_CFG_ADDR 0x0000
#define ADA_DMA_RDLR_OFFSET 16
#define ADA_DMA_RDLR_MASK 0x0FFF0000
#define ADA_DMA_TDLR_OFFSET 4
#define ADA_DMA_TDLR_MASK 0x0000FFF0
#define ADC_EN_OFFSET 3
#define ADC_EN_MASK 0x00000008
#define DAC_EN_OFFSET 2
#define DAC_EN_MASK 0x00000004
#define ADA_MEM_EB_OFFSET 1
#define ADA_MEM_EB_MASK 0x00000002
#define ADA_DMA_EB_OFFSET 0
#define ADA_DMA_EB_MASK 0x00000001

//-----------------------------------
#define CFG_ADA_ADC_CFG0_ADDR 0x0004
#define ADC_BYTES_SELECT_OFFSET 11
#define ADC_BYTES_SELECT_MASK 0x00001800
#define ADC_DUMP_SPEED_OFFSET 8
#define ADC_DUMP_SPEED_MASK 0x00000700
#define ADC_CLK_RATIO_OFFSET 4
#define ADC_CLK_RATIO_MASK 0x000000F0
#define ADC_DMSB_INV_OFFSET 3
#define ADC_DMSB_INV_MASK 0x00000008
#define ADC_DUMP_TRIG_POS_OFFSET 2
#define ADC_DUMP_TRIG_POS_MASK 0x00000004
#define ADC_DUMP_MODE_OFFSET 0
#define ADC_DUMP_MODE_MASK 0x00000003

//-----------------------------------
#define CFG_ADA_ADC_CFG1_ADDR 0x0008
#define ADC_SAMPLE_SIZE_OFFSET 0
#define ADC_SAMPLE_SIZE_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_ADA_ADC_CFG2_ADDR 0x000C
#define ADC_BUF_SIZE_OFFSET 0
#define ADC_BUF_SIZE_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_ADA_ADC_CFG3_ADDR 0x0010
#define ADC_DUMP_DONE_OFFSET 1
#define ADC_DUMP_DONE_MASK 0x00000002
#define ADC_SAMPLE_CNT_CLR_OFFSET 0
#define ADC_SAMPLE_CNT_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_ADA_ADC_CFG4_ADDR 0x0014
#define ADC_THRS_VAL_OFFSET 0
#define ADC_THRS_VAL_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_ADA_ADC_CFG5_ADDR 0x0018
#define ADC_TRIG_ADDR_OFFSET 0
#define ADC_TRIG_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_ADA_DAC_CFG0_ADDR 0x001C
#define DAC_CLK_RATIO_OFFSET 4
#define DAC_CLK_RATIO_MASK 0x000000F0
#define DAC_RAM_READ_DONE_OFFSET 3
#define DAC_RAM_READ_DONE_MASK 0x00000008
#define DAC_INIT_OFFSET 2
#define DAC_INIT_MASK 0x00000004
#define DAC_BYTES_SELECT_OFFSET 0
#define DAC_BYTES_SELECT_MASK 0x00000003

//-----------------------------------
#define CFG_ADA_DAC_CFG1_ADDR 0x0020
#define DAC_BUF_SIZE_OFFSET 0
#define DAC_BUF_SIZE_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_ADA_ADC_CFG6_ADDR 0x0024
#define ADC_ADDR_OFFSET_EN_OFFSET 30
#define ADC_ADDR_OFFSET_EN_MASK 0x40000000
#define ADC_ADDR_OFFSET_OFFSET 0
#define ADC_ADDR_OFFSET_MASK 0x3FFFFFFF

//-----------------------------------
#define CFG_ADA_DUMP_INT_RAW_ADDR 0x0050
#define DAC_RAM_READ_DONE_INT_RAW_OFFSET 2
#define DAC_RAM_READ_DONE_INT_RAW_MASK 0x00000004
#define ADC_SAMPLE_DONE_INT_RAW_OFFSET 1
#define ADC_SAMPLE_DONE_INT_RAW_MASK 0x00000002
#define ADA_DUMP_FIFO_FULL_INT_RAW_OFFSET 0
#define ADA_DUMP_FIFO_FULL_INT_RAW_MASK 0x00000001

//-----------------------------------
#define CFG_ADA_DUMP_INT_ST_ADDR 0x0054
#define DAC_RAM_READ_DONE_INT_ST_OFFSET 2
#define DAC_RAM_READ_DONE_INT_ST_MASK 0x00000004
#define ADC_SAMPLE_DONE_INT_ST_OFFSET 1
#define ADC_SAMPLE_DONE_INT_ST_MASK 0x00000002
#define ADA_DUMP_FIFO_FULL_INT_ST_OFFSET 0
#define ADA_DUMP_FIFO_FULL_INT_ST_MASK 0x00000001

//-----------------------------------
#define CFG_ADA_DUMP_INT_ENA_ADDR 0x0058
#define DAC_RAM_READ_DONE_INT_ENA_OFFSET 2
#define DAC_RAM_READ_DONE_INT_ENA_MASK 0x00000004
#define ADC_SAMPLE_DONE_INT_ENA_OFFSET 1
#define ADC_SAMPLE_DONE_INT_ENA_MASK 0x00000002
#define ADA_DUMP_FIFO_FULL_INT_ENA_OFFSET 0
#define ADA_DUMP_FIFO_FULL_INT_ENA_MASK 0x00000001

//-----------------------------------
#define CFG_ADA_DUMP_INT_CLR_ADDR 0x005C
#define DAC_RAM_READ_DONE_INT_CLR_OFFSET 2
#define DAC_RAM_READ_DONE_INT_CLR_MASK 0x00000004
#define ADC_SAMPLE_DONE_INT_CLR_OFFSET 1
#define ADC_SAMPLE_DONE_INT_CLR_MASK 0x00000002
#define ADA_DUMP_FIFO_FULL_INT_CLR_OFFSET 0
#define ADA_DUMP_FIFO_FULL_INT_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_ADA_TX_BUF_ADDR 0x0100
#define ADA_FIFO_WDATA_OFFSET 0
#define ADA_FIFO_WDATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_ADA_RX_BUF_ADDR 0x0180
#define ADA_FIFO_RDATA_OFFSET 0
#define ADA_FIFO_RDATA_MASK 0xFFFFFFFF

//HW module read/write macro
#define ADA_READ_REG(addr) SOC_READ_REG(ADA_DUMP_BASEADDR + addr)
#define ADA_WRITE_REG(addr,value) SOC_WRITE_REG(ADA_DUMP_BASEADDR + addr,value)