/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/
#include "phy_agc.h"
#include "iot_config.h"
#include "iot_errno_api.h"
#include "iot_io_api.h"
#include "phy_dfe_reg.h"
#include "phy_reg.h"
#include "hw_reg_api.h"
#include "hw_tonemask.h"
#include "phy_tx_reg.h"
#include "phy_txrx_pwr.h"
#include "phy_chn.h"

void phy_agc_adc_data_set(bool_t ena, uint8_t data)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_DFE_READ_REG(CFG_BB_AGC_SWCFG_EN_ADDR);
    REG_FIELD_SET( SW_GAIN_CFG_EN, tmp, ena );
    PHY_DFE_WRITE_REG(CFG_BB_AGC_SWCFG_EN_ADDR, tmp);

    tmp = PHY_DFE_READ_REG(CFG_GAIN_SERIAL_CFG0_ADDR);
    REG_FIELD_SET( SW_GAIN_CFG0_DATA, tmp, data << 4 );
    PHY_DFE_WRITE_REG(CFG_GAIN_SERIAL_CFG0_ADDR, tmp);
#else
    (void)ena;
    (void)data;
#endif
}

void phy_tx_pwr_ctl_en( \
    bool_t fd_en, bool_t td_en, bool_t ana_en)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_TX_READ_REG(CFG_BB_TX_PWR_FROM_MAC_CTRL_ADDR);
    REG_FIELD_SET( SW_TX_PWR_FD_FROM_TX_DESC, tmp, fd_en );
    REG_FIELD_SET( SW_TX_PWR_TD_FROM_TX_DESC, tmp, td_en );
    REG_FIELD_SET( SW_TX_PWR_ANA_FROM_TX_DESC, tmp, ana_en );
    PHY_TX_WRITE_REG(CFG_BB_TX_PWR_FROM_MAC_CTRL_ADDR, tmp);
#else
    (void)fd_en;
    (void)td_en;
    (void)ana_en;
#endif
}

void phy_gain_chg_rst_en_set(uint8_t rst)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_DFE_READ_REG(CFG_BB_DFE_RESET_CTRL_ADDR);
    REG_FIELD_SET( SW_GAIN_CHG_RST, tmp, rst );
    PHY_DFE_WRITE_REG(CFG_BB_DFE_RESET_CTRL_ADDR, tmp);
#else
    (void)rst;
#endif
}