/****************************************************************************
 *
 * Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
 *
 * This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
 * be copied by any method or incorporated into another program without
 * the express written consent of Aerospace C.Power. This Information or any portion
 * thereof remains the property of Aerospace C.Power. The Information contained herein
 * is believed to be accurate and Aerospace C.Power assumes no responsibility or
 * liability for its use in any way and conveys no license or title under
 * any patent or copyright and makes no representation or warranty that this
 * Information is free from patent or copyright infringement.
 *
 * ****************************************************************************/
/* os shim includes */
#include "os_types.h"
#include "iot_irq.h"
#include "iot_wdg.h"
#include "os_mem.h"
#include "efuse.h"
#include "iot_system.h"
#include "iot_io.h"

#include "platform.h"
#include "encoding.h"

extern void def_trap_entry_2();
extern void intc_handler(uint32_t cpu);

cpu_state g_cpu1_state;

static void exception_handler_2(uintptr_t mcause, uintptr_t epc, saved_registers *reg)
{
    /* save cpu1's crash state */
    g_cpu1_state.crash = 1;
    g_cpu1_state.mcause = mcause;
    g_cpu1_state.mepc = epc;
    g_cpu1_state.trap_frame  = reg;

    while(1);
}

uintptr_t handle_trap_2(uintptr_t mcause, uintptr_t epc, saved_registers *reg)
{
    if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT) {
        intc_handler(HAL_INTR_CPU_1);
    }else {
        exception_handler_2(mcause, epc, reg);
    }

    return epc;
}

void _init_2()
{
    write_csr(mtvec, &def_trap_entry_2);

    clear_csr(mie, MIP_MEIP);
    clear_csr(mie, MIP_MTIP);

    iot_interrupt_init(HAL_INTR_CPU_1);

    set_csr(mie, MIP_MEIP);

    // Enable interrupts in general.
    set_csr(mstatus, MSTATUS_MIE);
    wdg_deinit(HAL_WDG_CPU_1);

    g_cpu1_state.flags = CPU_FLAG_RUNNING;
}

void _fini()
{

}

void assert_failed( unsigned char *pucFile, unsigned long ulLine )
{
    ( void ) pucFile;
    ( void ) ulLine;

    g_cpu1_state.assert_failed = 1;
    if (pucFile) {
        os_mem_cpy(g_cpu1_state.assert_info.file, pucFile, 32);
    } else {
        os_mem_set(g_cpu1_state.assert_info.file, 0, 32);
    }
    g_cpu1_state.assert_info.line = ulLine;

    /* do a breakpoint exception */
    asm volatile("ebreak");
}

void assert_failed_simple()
{
    g_cpu1_state.assert_failed = 1;
    os_mem_set(g_cpu1_state.assert_info.file, 0, 32);
    g_cpu1_state.assert_info.line = 0;

    /* do a breakpoint exception */
    asm volatile("ebreak");
}