#ifndef CHIP_REG_BASE_H
#define CHIP_REG_BASE_H

/* --------------- reg type --------------- */
#define AHB_REG_LITE_BASEADDR          0x50019000
#define AHB_REG_LITE_SET_BASEADDR      0x50019400
#define AHB_REG_LITE_CLR_BASEADDR      0x50019800
#define RGF_MAC_BASEADDR               0x51000000
#define RGF_TMR_BASEADDR               0x51001000
#define RGF_HWQ_BASEADDR               0x51002000
#define RGF_RX_BASEADDR                0x51003000
#define RGF_RAW_BASEADDR               0x51004000
#define PHY_BASEADDR                   0x51800000
#define PHY_TX_BASEADDR                0x51900000
#define PHY_RXTD_BASEADDR              0x51A00000
#define PHY_RX_FD_BASEADDR             0x51B00000
#define PHY_DFE_BASEADDR               0x51C00000
#define PHY_ANA_BASEADDR               0x51D00000
#define DMA0_BASEADDR                  0x54000000
#define DMA1_BASEADDR                  0x5B000000
#define DMA2_BASEADDR                  0x5C000000
#define ADA_DUMP_BASEADDR              0x55000000
#define AHB_MTX_REG_BASEADDR           0x56000000
#define ICACHE0_REG_BASEADDR           0x58000000
#define ICACHE1_REG_BASEADDR           0x58010000
#define ICACHE2_REG_BASEADDR           0x58020000
#define DCACHE0_REG_BASEADDR           0x58030000
#define DCACHE1_REG_BASEADDR           0x58040000
#define RSA0_REG_BASEADDR              0x58051000
#define DES0_REG_BASEADDR              0x58052000
#define SM40_REG_BASEADDR              0x58053000
#define AES0_REG_BASEADDR              0x58054000
#define CRC0_REG_BASEADDR              0x58057000
#define TRNG_REG_BASEADDR              0x58056000
#define SEC0_SYS_REG_BASEADDR          0x58050000
#define SEC_AES_REG_BASEADDR           0x58060000
#define SEC_SM4_REG_BASEADDR           0x58070000
#define SFC_REG_BASEADDR               0x58080100
#define SMC_REG_BASEADDR               0x58080200
#define USB_MAC_REG_BASEADDR           0x57000000
#define USB_PHY_REG_BASEADDR           0x57100000
#define GMAC_REG_BASEADDR              0x59000000
#define AFFT_REG_BASEADDR              0x5a000000
#define EQ_REG_BASEADDR                0x5a020000
#define APB_REG_LITE_BASEADDR          0x40000000
#define APB_REG_LITE_SET_BASEADDR      0x40000400
#define APB_REG_LITE_CLR_BASEADDR      0x40000800
#define GPIO_BASEADDR                  0x40002000
#define SPINLOCK_REG_BASEADDR          0x40003000
#define DIG_PIN_REG_BASEADDR           0x40004000
#define FMST_REG_BASEADDR              0x40005000
#define GPIO_MTX_REG_BASEADDR          0x40006000
#define LEDC_REG_BASEADDR              0x40007000
#define LEDC_FREE_REG_BASEADDR         0x40081000
#define MAILBOX_REG_BASEADDR           0x40008000
#define ANA_DIG_WRAP_BASEADDR          0x40009000
#define APB_UART0_BASEADDR             0x40010000
#define APB_UART1_BASEADDR             0x40011000
#define APB_UART2_BASEADDR             0x40012000
#define APB_UART3_BASEADDR             0x40013000
#define APB_UART4_BASEADDR             0x40014000
#define APB_UART5_BASEADDR             0x40015000
#define APB_UART6_BASEADDR             0x40016000
#define APB_UART7_BASEADDR             0x40017000
#define GTMR0_BASEADDR                 0x40020000
#define GTMR1_BASEADDR                 0x40021000
#define GTMR2_BASEADDR                 0x40022000
#define INTC0_BASEADDR                 0x40030000
#define INTC1_BASEADDR                 0x40031000
#define INTC2_BASEADDR                 0x40032000
#define WDG0_REG_BASEADDR              0x40040000
#define WDG1_REG_BASEADDR              0x40041000
#define WDG2_REG_BASEADDR              0x40042000
#define I2C_M0_REG_BASEADDR            0x40050000
#define I2C_M1_REG_BASEADDR            0x40051000
#define I2C_M2_REG_BASEADDR            0x40052000
#define I2C_M3_REG_BASEADDR            0x40053000
#define SPI_M0_REG_BASEADDR            0x40060000
#define SPI_M1_REG_BASEADDR            0x40061000
#define SPI_M2_REG_BASEADDR            0x40062000
#define SPI_M3_REG_BASEADDR            0x40063000
#define SPI_S0_REG_BASEADDR            0x40064000
#define TPID_BASEADDR                  0x580A0000
#define SADC_BASEADDR                  0x58090000
#define PLL_CAL_BASEADDR               0x40067000
#define EFUSE_BASEADDR                 0x40068000
#define RTC_TMR0_BASEADDR              0x40069000
#define PWM0_REG_BASEADDR              0x40070000
#define PWM1_REG_BASEADDR              0x40071000
#define PWM2_REG_BASEADDR              0x40072000
#define PWM3_REG_BASEADDR              0x40073000
#define PWM4_REG_BASEADDR              0x40074000
#define PWM5_REG_BASEADDR              0x40075000
#define BOND_REG_BASEADDR              0x40080000

/* --------------- ram type --------------- */
#define AHB_RAM0_BASEADDR              0x10000000
#define AHB_RAM1_BASEADDR              0x10020000
#define AHB_RAM2_BASEADDR              0x10040000
#define AHB_RAM3_BASEADDR              0x10060000
#define DCACHE1_REMAP_BASEADDR         0x10070000
#define ICACHE0_SMC_RAM_BASEADDR       0x20000000
#define ICACHE0_SFC_RAM_BASEADDR       0x24000000
#define ICACHE1_SMC_RAM_BASEADDR       0x30000000
#define ICACHE1_SFC_RAM_BASEADDR       0x34000000
#define ICACHE2_SMC_RAM_BASEADDR       0x60000000
#define ICACHE2_SFC_RAM_BASEADDR       0x64000000
#define DCACHE0_SMC_RAM_BASEADDR       0x70000000
#define DCACHE0_SFC_RAM_BASEADDR       0x74000000
#define DCACHE1_SMC_RAM_BASEADDR       0x80000000
#define DCACHE1_SFC_RAM_BASEADDR       0x84000000
#define SFC_MEM_BASEADDR               0x58084000

/* --------------- rom type --------------- */
#define AHB_ROM_BASEADDR               0x00020000

/* --------------- cfg type --------------- */
#define RFPLC_SYS_BASEADDR             0x52000000

/* --------------- end address type --------------- */
#define AHB_ROM_ENDADDR                0x0005FFFF
#define AHB_RAM0_ENDADDR               0x1001FFFF
#define AHB_RAM1_ENDADDR               0x1003FFFF
#define AHB_RAM2_ENDADDR               0x1005FFFF
#define AHB_RAM3_ENDADDR               0x1006FFFF
#define DCACHE1_REMAP_ENDADDR          0x1007FFFF
#define ICACHE0_SMC_RAM_ENDADDR        0x203FFFFF
#define ICACHE0_SFC_RAM_ENDADDR        0x243FFFFF
#define ICACHE1_SMC_RAM_ENDADDR        0x303FFFFF
#define ICACHE1_SFC_RAM_ENDADDR        0x343FFFFF
#define ICACHE2_SMC_RAM_ENDADDR        0x603FFFFF
#define ICACHE2_SFC_RAM_ENDADDR        0x643FFFFF
#define DCACHE0_SMC_RAM_ENDADDR        0x703FFFFF
#define DCACHE0_SFC_RAM_ENDADDR        0x743FFFFF
#define DCACHE1_SMC_RAM_ENDADDR        0x803FFFFF
#define DCACHE1_SFC_RAM_ENDADDR        0x843FFFFF
#define RFPLC_SYS_ENDADDR              0x52FFFFFF

#endif