//-----------------------------------
#define CFG_LEDC_PROT_REG_ADDR 0x0004
#define LEDC_REG_PROT_ENABLE_OFFSET 16
#define LEDC_REG_PROT_ENABLE_MASK 0x00010000
#define LEDC_REG_PROT_PATTERN_OFFSET 0
#define LEDC_REG_PROT_PATTERN_MASK 0x0000FFFF

//-----------------------------------
#define CFG_LEDC_COMMON_DUTY_CNT_ADDR 0x0008
#define LEDC_COMMON_DUTY_CNT_THRS_OFFSET 16
#define LEDC_COMMON_DUTY_CNT_THRS_MASK 0xFFFF0000
#define LEDC_RDATA_SAMPLE_ENA_OFFSET 9
#define LEDC_RDATA_SAMPLE_ENA_MASK 0x00000200
#define LEDC_COMMON_DUTY_CNT_ENA_OFFSET 8
#define LEDC_COMMON_DUTY_CNT_ENA_MASK 0x00000100
#define LEDC_COMMON_TIMER_SEL_OFFSET 0
#define LEDC_COMMON_TIMER_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_LEDC0_CONF_ADDR 0x0200
#define LEDC0_DUTY_RELOAD_NOP_OFFSET 16
#define LEDC0_DUTY_RELOAD_NOP_MASK 0xFFFF0000
#define LEDC0_RDATA_SEL_EN_OFFSET 10
#define LEDC0_RDATA_SEL_EN_MASK 0x00000400
#define LEDC0_OUT_INV_OFFSET 9
#define LEDC0_OUT_INV_MASK 0x00000200
#define LEDC0_IDLE_LV_OFFSET 8
#define LEDC0_IDLE_LV_MASK 0x00000100
#define LEDC0_TIMER_SEL_OFFSET 0    // 每个通道使用公共定时器的时候可以选择定时器？
#define LEDC0_TIMER_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_LEDC0_DUTY_CONF0_ADDR 0x0204
#define LEDC0_DUTY_H2L_POINT_OFFSET 16
#define LEDC0_DUTY_H2L_POINT_MASK 0xFFFF0000
#define LEDC0_DUTY_L2H_POINT_OFFSET 0
#define LEDC0_DUTY_L2H_POINT_MASK 0x0000FFFF

//-----------------------------------
#define CFG_LEDC0_DUTY_CONF1_ADDR 0x0208
#define LEDC0_DUTY_CNT_SEL_OFFSET 28
#define LEDC0_DUTY_CNT_SEL_MASK 0x10000000
#define LEDC0_DUTY_MODE_OFFSET 26
#define LEDC0_DUTY_MODE_MASK 0x0C000000
#define LEDC0_DUTY_ENA_OFFSET 25
#define LEDC0_DUTY_ENA_MASK 0x02000000
#define LEDC0_DUTY_SCALE_OFFSET 16
#define LEDC0_DUTY_SCALE_MASK 0x00FF0000
#define LEDC0_DUTY_THRS_OFFSET 0
#define LEDC0_DUTY_THRS_MASK 0x0000FFFF

//-----------------------------------
#define CFG_LEDC0_DUTY_CONF2_ADDR 0x020C
#define LEDC0_DUTY_NUM_CNT_RELOAD_OFFSET 16
#define LEDC0_DUTY_NUM_CNT_RELOAD_MASK 0x00010000
#define LEDC0_DUTY_NUM_CNT_RELOAD_VAL_OFFSET 0
#define LEDC0_DUTY_NUM_CNT_RELOAD_VAL_MASK 0x0000FFFF

//-----------------------------------
#define CFG_LEDC0_DUTY_CONF3_ADDR 0x0210
#define LEDC0_DUTY_PHASE_NUM_OFFSET 16
#define LEDC0_DUTY_PHASE_NUM_MASK 0xFFFF0000
#define LEDC0_DUTY_NUM_OFFSET 0
#define LEDC0_DUTY_NUM_MASK 0x0000FFFF

//-----------------------------------
#define CFG_LEDC0_INT_ADDR 0x0214
#define LEDC0_DUTY_PHASE_RELOAD_INT_ST_OFFSET 22
#define LEDC0_DUTY_PHASE_RELOAD_INT_ST_MASK 0x00400000
#define LEDC0_NOP_INT_ST_OFFSET 21
#define LEDC0_NOP_INT_ST_MASK 0x00200000
#define LEDC0_DUTY_PHASE_RELOAD_INT_RAW_OFFSET 20
#define LEDC0_DUTY_PHASE_RELOAD_INT_RAW_MASK 0x00100000
#define LEDC0_NOP_INT_RAW_OFFSET 19
#define LEDC0_NOP_INT_RAW_MASK 0x00080000
#define LEDC0_DUTY_PHASE_RELOAD_INT_ENA_OFFSET 18
#define LEDC0_DUTY_PHASE_RELOAD_INT_ENA_MASK 0x00040000
#define LEDC0_NOP_INT_ENA_OFFSET 17
#define LEDC0_NOP_INT_ENA_MASK 0x00020000
#define LEDC0_DUTY_PHASE_RELOAD_INT_CLR_OFFSET 16
#define LEDC0_DUTY_PHASE_RELOAD_INT_CLR_MASK 0x00010000
#define LEDC0_NOP_INT_CLR_OFFSET 15
#define LEDC0_NOP_INT_CLR_MASK 0x00008000
#define LEDC0_SHADOW_INT_CLR_OFFSET 14
#define LEDC0_SHADOW_INT_CLR_MASK 0x00004000
#define LEDC0_DUTY_NUM_CNT_RELOAD_INT_CLR_OFFSET 13
#define LEDC0_DUTY_NUM_CNT_RELOAD_INT_CLR_MASK 0x00002000
#define LEDC0_DONE_INT_CLR_OFFSET 12
#define LEDC0_DONE_INT_CLR_MASK 0x00001000
#define LEDC0_SHADOW_INT_ENA_OFFSET 10
#define LEDC0_SHADOW_INT_ENA_MASK 0x00000400
#define LEDC0_DUTY_NUM_CNT_RELOAD_INT_ENA_OFFSET 9
#define LEDC0_DUTY_NUM_CNT_RELOAD_INT_ENA_MASK 0x00000200
#define LEDC0_DONE_INT_ENA_OFFSET 8
#define LEDC0_DONE_INT_ENA_MASK 0x00000100
#define LEDC0_SHADOW_INT_ST_OFFSET 6
#define LEDC0_SHADOW_INT_ST_MASK 0x00000040
#define LEDC0_DUTY_NUM_CNT_RELOAD_INT_ST_OFFSET 5
#define LEDC0_DUTY_NUM_CNT_RELOAD_INT_ST_MASK 0x00000020
#define LEDC0_DONE_INT_ST_OFFSET 4
#define LEDC0_DONE_INT_ST_MASK 0x00000010
#define LEDC0_SHADOW_INT_RAW_OFFSET 2
#define LEDC0_SHADOW_INT_RAW_MASK 0x00000004
#define LEDC0_DUTY_NUM_CNT_RELOAD_INT_RAW_OFFSET 1
#define LEDC0_DUTY_NUM_CNT_RELOAD_INT_RAW_MASK 0x00000002
#define LEDC0_DONE_INT_RAW_OFFSET 0
#define LEDC0_DONE_INT_RAW_MASK 0x00000001

//-----------------------------------
#define CFG_LEDC0_DUTY_CONF4_ADDR 0x0218
#define LEDC0_DUTY_CYCLE_NUM_OFFSET 24
#define LEDC0_DUTY_CYCLE_NUM_MASK 0xFF000000
#define LEDC0_DUTY_LOOP_NUM_OFFSET 16
#define LEDC0_DUTY_LOOP_NUM_MASK 0x00FF0000
#define LEDC0_DUTY_NOP_NUM_OFFSET 0
#define LEDC0_DUTY_NOP_NUM_MASK 0x0000FFFF

//-----------------------------------
#define CFG_LEDC0_DUTY_CONF5_ADDR 0x021C
#define LEDC0_DUTY_PHASE_RELOAD_OFFSET 31
#define LEDC0_DUTY_PHASE_RELOAD_MASK 0x80000000
#define LEDC0_DUTY_PHASE_OPT_OFFSET 29
#define LEDC0_DUTY_PHASE_OPT_MASK 0x20000000
#define LEDC0_DUTY_PHASE_MODE_NUM_OFFSET 28
#define LEDC0_DUTY_PHASE_MODE_NUM_MASK 0x10000000
#define LEDC0_DUTY_PHASE_MODE_OFFSET 24
#define LEDC0_DUTY_PHASE_MODE_MASK 0x0F000000
#define LEDC0_DUTY_PHASE_SCALE_OFFSET 16
#define LEDC0_DUTY_PHASE_SCALE_MASK 0x00FF0000
#define LEDC0_DUTY_RELOAD_LOOP_OFFSET 8
#define LEDC0_DUTY_RELOAD_LOOP_MASK 0x0000FF00
#define LEDC0_DUTY_RELOAD_CYCLE_OFFSET 0
#define LEDC0_DUTY_RELOAD_CYCLE_MASK 0x000000FF

//-----------------------------------
#define CFG_LEDC_TIMER0_CONF_ADDR 0x0600
#define LEDC_TIMER0_PAUSE_OFFSET 18
#define LEDC_TIMER0_PAUSE_MASK 0x00040000
#define LEDC_TIMER0_START_OFFSET 17
#define LEDC_TIMER0_START_MASK 0x00020000
#define LEDC_TIMER0_RST_OFFSET 16
#define LEDC_TIMER0_RST_MASK 0x00010000
#define LEDC_TIMER0_DIV_OFFSET 0
#define LEDC_TIMER0_DIV_MASK 0x0000FFFF

//-----------------------------------
#define CFG_LEDC_TIMER0_RELOAD_ADDR 0x0604
#define LEDC_TIMER0_RELOAD_OFFSET 16
#define LEDC_TIMER0_RELOAD_MASK 0x00010000
#define LEDC_TIMER0_RELOAD_VAL_OFFSET 0
#define LEDC_TIMER0_RELOAD_VAL_MASK 0x0000FFFF

//-----------------------------------
#define CFG_LEDC_TIMER0_STATUS_ADDR 0x0608
#define LEDC_TIMER0_CNT_OFFSET 0
#define LEDC_TIMER0_CNT_MASK 0x0000FFFF

//-----------------------------------
#define CFG_LEDC_TIMER0_INT_ADDR 0x060C
#define LEDC_TIMER0_RELOAD_INT_CLR_OFFSET 25
#define LEDC_TIMER0_RELOAD_INT_CLR_MASK 0x02000000
#define LEDC_TIMER0_OVF_INT_CLR_OFFSET 24
#define LEDC_TIMER0_OVF_INT_CLR_MASK 0x01000000
#define LEDC_TIMER0_RELOAD_INT_ENA_OFFSET 17
#define LEDC_TIMER0_RELOAD_INT_ENA_MASK 0x00020000
#define LEDC_TIMER0_OVF_INT_ENA_OFFSET 16
#define LEDC_TIMER0_OVF_INT_ENA_MASK 0x00010000
#define LEDC_TIMER0_RELOAD_INT_ST_OFFSET 9
#define LEDC_TIMER0_RELOAD_INT_ST_MASK 0x00000200
#define LEDC_TIMER0_OVF_INT_ST_OFFSET 8
#define LEDC_TIMER0_OVF_INT_ST_MASK 0x00000100
#define LEDC_TIMER0_RELOAD_INT_RAW_OFFSET 1
#define LEDC_TIMER0_RELOAD_INT_RAW_MASK 0x00000002
#define LEDC_TIMER0_OVF_INT_RAW_OFFSET 0
#define LEDC_TIMER0_OVF_INT_RAW_MASK 0x00000001

//HW module read/write macro
#define LEDC0_READ_REG(addr) SOC_READ_REG(LEDC_REG_BASEADDR + addr)
#define LEDC0_WRITE_REG(addr,value) SOC_WRITE_REG(LEDC_REG_BASEADDR + addr,value)

#define LEDC1_READ_REG(addr) SOC_READ_REG(LEDC_FREE_REG_BASEADDR + addr)
#define LEDC1_WRITE_REG(addr,value) SOC_WRITE_REG(LEDC_FREE_REG_BASEADDR + addr,value)