/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/

/* os shim includes */
#include "os_types.h"
#include "os_utils.h"
/* public api includes */
#include "plc_fr.h"
#include "iot_io.h"
#include "hw_phy_api.h"
#include "iot_errno.h"

#if HW_PLATFORM >= HW_PLATFORM_FPGA
#include "hw_reg_api.h"
#include "rfplc_reg_base.h"
#include "rfplc_general_reg.h"
#include "rf_mac_custom_reg.h"
#include "rf_mac_reg.h"
#include "wmac_reg.h"
#include "mac_rf_common_hw.h"
#include "phy_txrx_pwr.h"
#include "phy_phase.h"
#include "mac_sys_reg.h"
#include "iot_clock.h"


/* define the time of reset pa 6ms, unit us */
#define MAC_RF_RESET_PA_TIME_US  6000

/* config set option */
void mac_rf_set_option(uint32_t option)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    REG_FIELD_SET(RF_MAC_SET_OPTION_STS, tmp, 1);
    REG_FIELD_SET(RF_MAC_SET_OPTION, tmp, option);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR, tmp);
}

/* config set channel */
void mac_rf_set_tobe_channel_id(uint32_t channel)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    REG_FIELD_SET(RF_MAC_SET_TOBE_CHANNEL_STS, tmp, 1);
    REG_FIELD_SET(RF_MAC_SET_TOBE_CHANNEL_ID, tmp, channel);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR, tmp);
}

void mac_rf_set_option_success()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    REG_FIELD_SET(RF_MAC_SET_OPTION_STS, tmp, 0);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR, tmp);
}

void mac_rf_set_channel_success()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    REG_FIELD_SET(RF_MAC_SET_TOBE_CHANNEL_STS, tmp, 0);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR, tmp);
}

uint32_t mac_rf_get_option_sts()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    return REG_FIELD_GET(RF_MAC_SET_OPTION_STS, tmp);
}

uint32_t mac_rf_get_channel_sts()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    return REG_FIELD_GET(RF_MAC_SET_TOBE_CHANNEL_STS, tmp);
}

uint32_t mac_rf_get_option()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    return REG_FIELD_GET(RF_MAC_SET_OPTION, tmp);
}

uint32_t mac_rf_get_tobe_set_channel_id()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    return REG_FIELD_GET(RF_MAC_SET_TOBE_CHANNEL_ID, tmp);
}

uint32_t mac_rf_get_cur_channel_freq()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_CURRENT_CHANNEL_FREQ_ADDR);
    return REG_FIELD_GET(RF_MAC_CUR_CHANNEL_FREQ, tmp);
}

void mac_rf_set_cur_channel_freq(uint32_t channel_freq)
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_CURRENT_CHANNEL_FREQ_ADDR);
    REG_FIELD_SET(RF_MAC_CUR_CHANNEL_FREQ, tmp, channel_freq);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_CURRENT_CHANNEL_FREQ_ADDR, tmp);
}

uint32_t mac_rf_get_cur_channel_id()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_CURRENT_CHANNEL_ID_ADDR);
    return REG_FIELD_GET(RF_MAC_CUR_CHANNEL_ID, tmp);
}

void mac_rf_set_cur_channel_id(uint32_t channel_id)
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_CURRENT_CHANNEL_ID_ADDR);
    REG_FIELD_SET(RF_MAC_CUR_CHANNEL_ID, tmp, channel_id);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_CURRENT_CHANNEL_ID_ADDR, tmp);
}

uint32_t mac_rf_get_bbcpu_sts()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_BB_CPU_STS_ADDR);
    return REG_FIELD_GET(RF_MAC_BBCPU_STS, tmp);
}

void mac_rf_set_bbcpu_sts()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_BB_CPU_STS_ADDR);
    REG_FIELD_SET(RF_MAC_BBCPU_STS, tmp, 1);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_BB_CPU_STS_ADDR, tmp);
}

void IRAM_ATTR mac_rf_set_stop_sched_sts_start()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_BB_CPU_STS_ADDR);
    REG_FIELD_SET(RF_MAC_STOP_SCHED_STS, tmp, 1);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_BB_CPU_STS_ADDR, tmp);
}

void IRAM_ATTR mac_rf_set_stop_sched_sts_success()
{
    uint32_t tmp;
    phy_force_0_access_require_from_isr();
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_BB_CPU_STS_ADDR);
    REG_FIELD_SET(RF_MAC_STOP_SCHED_STS, tmp, 0);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_BB_CPU_STS_ADDR, tmp);
    phy_force_0_access_release_from_isr();
}

uint32_t IRAM_ATTR mac_rf_get_stop_sched_sts()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_BB_CPU_STS_ADDR);
    return REG_FIELD_GET(RF_MAC_STOP_SCHED_STS, tmp);
}

void mac_rf_use_wmac_enable(uint32_t enable)
{
    uint32_t tmp = RFPLC_GENERAL_READ_REG(CFG_RFPLC_WMAC_CTRL_ADDR);
    REG_FIELD_SET(SW_USE_WMAC, tmp, enable);
    RFPLC_GENERAL_WRITE_REG(CFG_RFPLC_WMAC_CTRL_ADDR, tmp);
}

uint32_t mac_rf_get_use_wmac_enable()
{
    uint32_t tmp = RFPLC_GENERAL_READ_REG(CFG_RFPLC_WMAC_CTRL_ADDR);
    return REG_FIELD_GET(SW_USE_WMAC, tmp);
}

void mac_rf_reset_txrxfsm()
{
    uint32_t tmp = WMAC_READ_REG(CFG_WMAC_FSM_SRST_ADDR);
    REG_FIELD_SET(SW_TRX_FSM_SRST, tmp, 1);
    WMAC_WRITE_REG(CFG_WMAC_FSM_SRST_ADDR, tmp);
}

uint32_t mac_rf_wmac_get_fsm()
{
    uint32_t wmac_fsm = WMAC_READ_REG(CFG_WMAC_TOP_FSM_STS_ADDR);
    return (wmac_fsm & 0xFFF);
}

void mac_rf_to_wphy_interface_init(uint8_t power_reset)
{
#if HW_PLATFORM == HW_PLATFORM_SILICON
    uint32_t tmp = RFPLC_GENERAL_READ_REG(CFG_RFPLC_DBG_CTRL_ADDR);
    REG_FIELD_SET(SW_EN_CALIB, tmp, 1);
    RFPLC_GENERAL_WRITE_REG(CFG_RFPLC_DBG_CTRL_ADDR, tmp);

    tmp = RFPLC_GENERAL_READ_REG(CFG_RFPLC_FCLK_CTRL_ADDR);
    REG_FIELD_SET(RFPLC_WAFE_TXNRX_INV_SEL, tmp, 0);
    REG_FIELD_SET(RFPLC_FCLK_INV_SEL, tmp, 0);
    RFPLC_GENERAL_WRITE_REG(CFG_RFPLC_FCLK_CTRL_ADDR, tmp);
    if (power_reset) {
        /* reset pa */
        mac_rf_disable_pa(1);
        iot_delay_us(MAC_RF_RESET_PA_TIME_US);
        mac_rf_disable_pa(0);
        iot_delay_us(1000);
    }
#endif
}

void mac_rf_set_spi_gpio(uint8_t clk_gpio, uint8_t cs_gpio, uint8_t mosi_gpio,
    uint8_t miso_gpio)
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_SPI_GPIO_ADDR);
    REG_FIELD_SET(RF_MAC_SPI_CLK, tmp, clk_gpio);
    REG_FIELD_SET(RF_MAC_SPI_CS, tmp, cs_gpio);
    REG_FIELD_SET(RF_MAC_SPI_MOSI, tmp, mosi_gpio);
    REG_FIELD_SET(RF_MAC_SPI_MISO, tmp, miso_gpio);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_SPI_GPIO_ADDR, tmp);
}

void mac_rf_get_spi_gpio(uint8_t *clk_gpio, uint8_t *cs_gpio,
    uint8_t *mosi_gpio, uint8_t *miso_gpio)
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_SPI_GPIO_ADDR);
    *clk_gpio = REG_FIELD_GET(RF_MAC_SPI_CLK, tmp);
    *cs_gpio = REG_FIELD_GET(RF_MAC_SPI_CS, tmp);
    *mosi_gpio = REG_FIELD_GET(RF_MAC_SPI_MOSI, tmp);
    *miso_gpio = REG_FIELD_GET(RF_MAC_SPI_MISO, tmp);
}

void mac_rf_set_cert_mode(uint32_t cert_mode)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_CERT_INFO_ADDR);
    REG_FIELD_SET(RF_MAC_CERT_MODE, tmp, cert_mode);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_CERT_INFO_ADDR, tmp);
}

uint32_t mac_rf_get_cert_mode()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_CERT_INFO_ADDR);
    return REG_FIELD_GET(RF_MAC_CERT_MODE, tmp);
}

void mac_rf_set_cert_16qam_flag(uint32_t special_cfg)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_CERT_INFO_ADDR);
    REG_FIELD_SET(RF_MAC_CERT_MCS56_FLAG, tmp, special_cfg);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_CERT_INFO_ADDR, tmp);
}

uint32_t mac_rf_get_cert_16qam_flag()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_CERT_INFO_ADDR);
    return REG_FIELD_GET(RF_MAC_CERT_MCS56_FLAG, tmp);
}

void mac_rf_set_cert_flag()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_CERT_INFO_ADDR);
    REG_FIELD_SET(RF_MAC_CERT_FLAG, tmp, 1);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_CERT_INFO_ADDR, tmp);
}

uint32_t mac_rf_get_cert_flag()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_CERT_INFO_ADDR);
    return REG_FIELD_GET(RF_MAC_CERT_FLAG, tmp);
}

void mac_rf_set_user_type(uint8_t user_type)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_CERT_INFO_ADDR);
    REG_FIELD_SET(RF_MAC_USER_TYPE, tmp, user_type);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_CERT_INFO_ADDR, tmp);
}

uint8_t mac_rf_get_user_type()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_CERT_INFO_ADDR);
    return REG_FIELD_GET(RF_MAC_USER_TYPE, tmp);
}

void mac_rf_set_hplc_rf_async_tx(uint32_t async_tx)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_CERT_INFO_ADDR);
    REG_FIELD_SET(RF_MAC_HPLC_RF_ASYNC_TX, tmp, async_tx);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_CERT_INFO_ADDR, tmp);
}

uint32_t mac_rf_get_hplc_rf_async_tx()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_CERT_INFO_ADDR);
    return REG_FIELD_GET(RF_MAC_HPLC_RF_ASYNC_TX, tmp);
}

uint32_t mac_rf_get_tx_start_cnt()
{
    return RF_MAX_CUS_READ_REG(CFG_RF_MAC_TX_START_CNT_ADDR);
}

void mac_rf_set_hplc_pcs_reg(uint32_t is_busy)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_NOTIFY_HPLC_INFO_1_ADDR);
    REG_FIELD_SET(RF_MAC_NOTIFY_HPLC_SET_PCS, tmp, is_busy);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_NOTIFY_HPLC_INFO_1_ADDR, tmp);
}

uint32_t IRAM_ATTR mac_rf_get_hplc_pcs_reg()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_NOTIFY_HPLC_INFO_1_ADDR);
    return REG_FIELD_GET(RF_MAC_NOTIFY_HPLC_SET_PCS, tmp);
}

void IRAM_ATTR mac_rf_set_hplc_pcs_sts_reg(uint32_t is_busy)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_NOTIFY_HPLC_INFO_2_ADDR);
    REG_FIELD_SET(RF_MAC_NOTIFY_HPLC_SET_PCS_STS, tmp, is_busy);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_NOTIFY_HPLC_INFO_2_ADDR, tmp);
}

uint32_t mac_rf_get_hplc_pcs_sts_reg()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_NOTIFY_HPLC_INFO_2_ADDR);
    return REG_FIELD_GET(RF_MAC_NOTIFY_HPLC_SET_PCS_STS, tmp);
}

void mac_rf_tx_start_cnt_inc()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TX_START_CNT_ADDR);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TX_START_CNT_ADDR, ++tmp);
}

uint32_t mac_rf_get_tx_ok_with_pld_cnt()
{
    return RF_MAX_CUS_READ_REG(CFG_RF_MAC_TX_OK_WITH_PLD_CNT_ADDR);
}

void mac_rf_tx_ok_with_pld_cnt_inc()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TX_OK_WITH_PLD_CNT_ADDR);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TX_OK_WITH_PLD_CNT_ADDR, ++tmp);
}

uint32_t mac_rf_get_tx_ok_without_pld_cnt()
{
    return RF_MAX_CUS_READ_REG(CFG_RF_MAC_TX_OK_WITHOUT_PLD_CNT_ADDR);
}

void mac_rf_tx_ok_without_pld_cnt_inc()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TX_OK_WITHOUT_PLD_CNT_ADDR);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TX_OK_WITHOUT_PLD_CNT_ADDR, ++tmp);
}

uint32_t mac_rf_get_rx_sig_ok_cnt()
{
    return RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_SIG_OK_CNT_ADDR);
}

void mac_rf_rx_sig_ok_cnt_inc()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_SIG_OK_CNT_ADDR);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_RX_SIG_OK_CNT_ADDR, ++tmp);
}

uint32_t mac_rf_get_rx_sig_err_cnt()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_SIG_STF_ESCEP_CNT_ADDR);
    return REG_FIELD_GET(RF_MAC_RX_SIG_ERR_CNT, tmp);
}

void mac_rf_rx_sig_err_cnt_inc()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_SIG_STF_ESCEP_CNT_ADDR);
    uint16_t rx_sig_err = REG_FIELD_GET(RF_MAC_RX_SIG_ERR_CNT, tmp);
    REG_FIELD_SET(RF_MAC_RX_SIG_ERR_CNT, tmp, ++rx_sig_err);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_RX_SIG_STF_ESCEP_CNT_ADDR, tmp);
}

uint32_t mac_rf_get_rx_phr_ok_with_pld_cnt()
{
    return RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_PHR_OK_WITH_PLD_CNT_ADDR);
}

void mac_rf_rx_phr_ok_with_pld_cnt_inc()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_PHR_OK_WITH_PLD_CNT_ADDR);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_RX_PHR_OK_WITH_PLD_CNT_ADDR, ++tmp);
}

uint32_t mac_rf_get_rx_phr_ok_without_pld_cnt()
{
    return RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_PHR_OK_WITHOUT_PLD_CNT_ADDR);
}

void mac_rf_rx_phr_ok_without_pld_cnt_inc()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_PHR_OK_WITHOUT_PLD_CNT_ADDR);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_RX_PHR_OK_WITHOUT_PLD_CNT_ADDR, ++tmp);
}

uint32_t mac_rf_get_rx_phr_err_cnt()
{
    return RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_PHR_ERR_CNT_ADDR);
}

void mac_rf_rx_phr_err_cnt_inc()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_PHR_ERR_CNT_ADDR);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_RX_PHR_ERR_CNT_ADDR, ++tmp);
}

uint32_t mac_rf_get_rx_pld_ok_cnt()
{
    return RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_PLD_OK_CNT_ADDR);
}

void mac_rf_rx_pld_ok_cnt_inc()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_PLD_OK_CNT_ADDR);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_RX_PLD_OK_CNT_ADDR, ++tmp);
}

uint32_t mac_rf_get_rx_pld_err_cnt()
{
    return RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_PLD_ERR_CNT_ADDR);
}

void mac_rf_rx_pld_err_cnt_inc()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_PLD_ERR_CNT_ADDR);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_RX_PLD_ERR_CNT_ADDR, ++tmp);
}

uint32_t mac_rf_get_rx_stf_cnt()
{
    return RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_STF_CNT_ADDR);
}

void mac_rf_rx_stf_cnt_inc()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_STF_CNT_ADDR);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_RX_STF_CNT_ADDR, ++tmp);
}

uint32_t mac_rf_get_lost_stf_cnt()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_SIG_STF_ESCEP_CNT_ADDR);
    return REG_FIELD_GET(RF_MAC_RX_LOST_STF_CNT, tmp);
}

void mac_rf_lost_stf_cnt_inc()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_SIG_STF_ESCEP_CNT_ADDR);
    uint16_t lost_stf = REG_FIELD_GET(RF_MAC_RX_LOST_STF_CNT, tmp);
    REG_FIELD_SET(RF_MAC_RX_LOST_STF_CNT, tmp, ++lost_stf);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_RX_SIG_STF_ESCEP_CNT_ADDR, tmp);
}

void mac_rf_record_dbg_cnt()
{
    phy_rx_cnt_t *phy_rx_info = &g_phy_ctxt.dep.phy_status.phy_rx_cnt;
    /* phy rf tx start cnt */
    phy_rx_info->phy_rf_tx_start_cnt = mac_rf_get_tx_start_cnt();
    /* phy rf tx ok with pld cnt */
    phy_rx_info->phy_rf_tx_ok_with_pld_cnt = mac_rf_get_tx_ok_with_pld_cnt();
    /* phy rf tx ok without pld cnt */
    phy_rx_info->phy_rf_tx_ok_without_pld_cnt =
        mac_rf_get_tx_ok_without_pld_cnt();
    /* phy rf rx stf cnt */
    phy_rx_info->phy_rf_rx_stf_cnt = mac_rf_get_rx_stf_cnt();
    /* phy rf rx sig ok cnt */
    phy_rx_info->phy_rf_rx_sig_ok_cnt = mac_rf_get_rx_sig_ok_cnt();
    /* phy rf rx sig error cnt */
    phy_rx_info->phy_rf_rx_sig_err_cnt = mac_rf_get_rx_sig_err_cnt();
    /* phy rf rx phr ok with pld cnt */
    phy_rx_info->phy_rf_rx_phr_ok_with_pld_cnt =
        mac_rf_get_rx_phr_ok_with_pld_cnt();
    /* phy rf rx phr ok without pld cnt */
    phy_rx_info->phy_rf_rx_phr_ok_without_pld_cnt =
        mac_rf_get_rx_phr_ok_without_pld_cnt();
    /* phy rf rx phr error cnt */
    phy_rx_info->phy_rf_rx_phr_err_cnt = mac_rf_get_rx_phr_err_cnt();
    /* phy rf rx pld ok cnt */
    phy_rx_info->phy_rf_rx_pld_ok_cnt = mac_rf_get_rx_pld_ok_cnt();
    /* phy rf rx pld error cnt */
    phy_rx_info->phy_rf_rx_pld_err_cnt = mac_rf_get_rx_pld_err_cnt();
    /* phy rf lost stf cnt */
    phy_rx_info->phy_rf_lost_stf_cnt = mac_rf_get_lost_stf_cnt();
}

void mac_rf_recover_dbg_cnt()
{
    phy_rx_cnt_t *phy_rx_info = &g_phy_ctxt.dep.phy_status.phy_rx_cnt;
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TX_START_CNT_ADDR,
        phy_rx_info->phy_rf_tx_start_cnt);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TX_OK_WITH_PLD_CNT_ADDR,
        phy_rx_info->phy_rf_tx_ok_with_pld_cnt);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TX_OK_WITHOUT_PLD_CNT_ADDR,
        phy_rx_info->phy_rf_tx_ok_without_pld_cnt);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_RX_STF_CNT_ADDR,
        phy_rx_info->phy_rf_rx_stf_cnt);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_RX_SIG_OK_CNT_ADDR,
        phy_rx_info->phy_rf_rx_sig_ok_cnt);
    /* recover rx sig err cnt */
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_RX_SIG_STF_ESCEP_CNT_ADDR);
    /* recover rx sig err cnt */
    REG_FIELD_SET(RF_MAC_RX_SIG_ERR_CNT, tmp,
        phy_rx_info->phy_rf_rx_sig_err_cnt);
    /* recover lost stf cnt */
    REG_FIELD_SET(RF_MAC_RX_LOST_STF_CNT, tmp,
        phy_rx_info->phy_rf_lost_stf_cnt);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_RX_SIG_STF_ESCEP_CNT_ADDR, tmp);

    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_RX_PHR_OK_WITH_PLD_CNT_ADDR,
        phy_rx_info->phy_rf_rx_phr_ok_with_pld_cnt);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TX_OK_WITHOUT_PLD_CNT_ADDR,
        phy_rx_info->phy_rf_rx_phr_ok_without_pld_cnt);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_RX_PHR_ERR_CNT_ADDR,
        phy_rx_info->phy_rf_rx_phr_err_cnt);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_RX_PLD_OK_CNT_ADDR,
        phy_rx_info->phy_rf_rx_pld_ok_cnt);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_RX_PLD_ERR_CNT_ADDR,
        phy_rx_info->phy_rf_rx_pld_err_cnt);
}

void mac_rf_set_tx_special_ldovs(uint16_t ldovs)
{
    uint32_t tmp;

    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI0_ADDR);
    REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_TX_SPECIAL_LDOVS, tmp, ldovs);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_CALI0_ADDR, tmp);
}

uint16_t mac_rf_get_tx_special_ldovs()
{
    uint32_t tmp;
    uint16_t ldovs;

    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI0_ADDR);
    ldovs = (uint16_t)REG_FIELD_GET(CFG_RF_MAC_TO_WPHY_TX_SPECIAL_LDOVS, tmp);

    return ldovs;
}

void mac_rf_set_tx_special_scale(uint16_t scale)
{
    uint32_t tmp;

    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI1_ADDR);
    REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_TX_SPECIAL_SCALE, tmp, scale);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_CALI1_ADDR, tmp);
}

uint16_t mac_rf_get_tx_special_scale()
{
    uint32_t tmp;
    uint16_t scale;

    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI1_ADDR);
    scale = (uint16_t)REG_FIELD_GET(CFG_RF_MAC_TO_WPHY_TX_SPECIAL_SCALE, tmp);

    return scale;
}

void mac_rf_set_tx_dc_cali(uint8_t tx_i_dc, uint8_t tx_q_dc)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI0_ADDR);
    REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_TX_I_DC, tmp, tx_i_dc);
    REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_TX_Q_DC, tmp, tx_q_dc);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_CALI0_ADDR, tmp);
}

void mac_rf_set_tx_filter_cali(uint8_t option, uint8_t en, uint16_t sel)
{
    uint32_t tmp;
    switch (option) {
    case RF_OPTION_1:
    {
        if (en) {
            tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI2_ADDR);
            REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_OPT1_BW_SEL_EN, tmp, 1);
            REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_OPT1_BW_SEL, tmp, sel);
            RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_CALI2_ADDR, tmp);
        } else {
            tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI2_ADDR);
            REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_OPT1_BW_SEL_EN, tmp, 0);
            RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_CALI2_ADDR, tmp);
        }
        break;
    }
    case RF_OPTION_2:
    {
         if (en) {
            tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI2_ADDR);
            REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_OPT2_BW_SEL_EN, tmp, 1);
            REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_OPT2_BW_SEL, tmp, sel);
            RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_CALI2_ADDR, tmp);
        } else {
            tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI2_ADDR);
            REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_OPT2_BW_SEL_EN, tmp, 0);
            RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_CALI2_ADDR, tmp);
        }
        break;
    }
    case RF_OPTION_3:
    {
         if (en) {
            tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI2_ADDR);
            REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_OPT3_BW_SEL_EN, tmp, 1);
            REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_OPT3_BW_SEL, tmp, sel);
            RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_CALI2_ADDR, tmp);
        } else {
            tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI2_ADDR);
            REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_OPT3_BW_SEL_EN, tmp, 0);
            RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_CALI2_ADDR, tmp);
        }

        break;
    }
    default:
        IOT_ASSERT(0);
        break;
    }

}

void mac_rf_set_tx_iqm_cali(uint8_t tx_i_m, uint8_t tx_q_m)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI1_ADDR);
    REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_TX_I_M, tmp, tx_i_m);
    REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_TX_Q_M, tmp, tx_q_m);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_CALI1_ADDR, tmp);
}

void mac_rf_set_tx_iqp_cali(uint8_t tx_i_p, uint8_t tx_q_p)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI1_ADDR);
    REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_TX_I_P, tmp, tx_i_p);
    REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_TX_Q_P, tmp, tx_q_p);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_CALI1_ADDR, tmp);
}

void mac_rf_get_tx_dc_cali(uint8_t *tx_i_dc, uint8_t *tx_q_dc)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI0_ADDR);
    *tx_i_dc = (uint8_t)REG_FIELD_GET(CFG_RF_MAC_TO_WPHY_TX_I_DC, tmp);
    *tx_q_dc = (uint8_t)REG_FIELD_GET(CFG_RF_MAC_TO_WPHY_TX_Q_DC, tmp);
}

void mac_rf_get_tx_iqm_cali(uint8_t *tx_i_m, uint8_t *tx_q_m)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI1_ADDR);
    *tx_i_m = (uint8_t)REG_FIELD_GET(CFG_RF_MAC_TO_WPHY_TX_I_M, tmp);
    *tx_q_m = (uint8_t)REG_FIELD_GET(CFG_RF_MAC_TO_WPHY_TX_Q_M, tmp);
}

void mac_rf_get_tx_iqp_cali(uint8_t *tx_i_p, uint8_t *tx_q_p)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI1_ADDR);
    *tx_i_p = (uint8_t)REG_FIELD_GET(CFG_RF_MAC_TO_WPHY_TX_I_P, tmp);
    *tx_q_p = (uint8_t)REG_FIELD_GET(CFG_RF_MAC_TO_WPHY_TX_Q_P, tmp);
}

void mac_rf_get_tx_filter_cali(uint8_t option, uint8_t *en, uint16_t *sel)
{
    uint32_t tmp;
    *en = 0;
    *sel = 0;
    switch (option) {
    case RF_OPTION_1:
    {
        tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI2_ADDR);
        *en = (uint8_t)REG_FIELD_GET(CFG_RF_MAC_TO_WPHY_OPT1_BW_SEL_EN, tmp);
        *sel = (uint16_t)REG_FIELD_GET(CFG_RF_MAC_TO_WPHY_OPT1_BW_SEL, tmp);
        break;
    }
    case RF_OPTION_2:
    {
        tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI2_ADDR);
        *en = (uint8_t)REG_FIELD_GET(CFG_RF_MAC_TO_WPHY_OPT2_BW_SEL_EN, tmp);
        *sel = (uint16_t)REG_FIELD_GET(CFG_RF_MAC_TO_WPHY_OPT2_BW_SEL, tmp);
        break;
    }
    case RF_OPTION_3:
    {
        tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI2_ADDR);
        *en = (uint8_t)REG_FIELD_GET(CFG_RF_MAC_TO_WPHY_OPT3_BW_SEL_EN, tmp);
        *sel = (uint16_t)REG_FIELD_GET(CFG_RF_MAC_TO_WPHY_OPT3_BW_SEL, tmp);
        break;
    }
    default:
        break;
    }
}

void mac_rf_set_rf_spi(uint16_t addr, uint16_t value)
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_SPI_CFG_ADDR);
    REG_FIELD_SET(RF_MAC_SET_SPI_ADDR, tmp, addr);
    REG_FIELD_SET(RF_MAC_SET_SPI_VALUE, tmp, value);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_SPI_CFG_ADDR, tmp);
}

void mac_rf_get_rf_spi(uint16_t *addr, uint16_t *value)
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_SPI_CFG_ADDR);
    *addr = REG_FIELD_GET(RF_MAC_SET_SPI_ADDR, tmp);
    *value = REG_FIELD_GET(RF_MAC_SET_SPI_VALUE, tmp);
}

void mac_rf_set_rf_spi_rw_cfg(uint32_t value)
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_SPI_STATUS_ADDR);
    REG_FIELD_SET(RF_MAC_SPI_R_W, tmp, value);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_SPI_STATUS_ADDR, tmp);
}

uint32_t mac_rf_get_rf_spi_rw_cfg()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_SPI_STATUS_ADDR);
    return REG_FIELD_GET(RF_MAC_SPI_R_W, tmp);
}

void mac_rf_set_rf_spi_status(uint32_t value)
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_SPI_STATUS_ADDR);
    REG_FIELD_SET(RF_MAC_CFG_SPI_STS, tmp, value);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_SPI_STATUS_ADDR, tmp);
}

uint32_t mac_rf_get_rf_spi_status()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_SPI_STATUS_ADDR);
    return REG_FIELD_GET(RF_MAC_CFG_SPI_STS, tmp);
}

void mac_rf_set_tx_cal_update_status(uint32_t value)
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_SPI_STATUS_ADDR);
    REG_FIELD_SET(RF_MAC_TX_CAL_UPDATE_STS, tmp, value);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_SPI_STATUS_ADDR, tmp);
}

uint32_t mac_rf_get_tx_cal_update_status()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_SPI_STATUS_ADDR);
    return REG_FIELD_GET(RF_MAC_TX_CAL_UPDATE_STS, tmp);
}

void mac_rf_set_rf_ver(uint32_t value)
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI1_ADDR);
    REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_RF_VER, tmp, value);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_CALI1_ADDR, tmp);
}

uint32_t mac_rf_get_rf_ver()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI1_ADDR);
    return REG_FIELD_GET(CFG_RF_MAC_TO_WPHY_RF_VER, tmp);
}

void mac_rf_tx_dc(uint32_t i_mag, uint32_t q_mag, uint32_t on_off)
{
    uint32_t tmp;

    /* clear rfplc contrl */
    RFPLC_GENERAL_WRITE_REG(CFG_RFPLC_DBG_CFG0_ADDR, 0);

    tmp = RFPLC_GENERAL_READ_REG(CFG_RFPLC_DBG_CFG1_ADDR);
    REG_FIELD_SET(SW_RFPLC_TX_DC_I, tmp, i_mag);
    REG_FIELD_SET(SW_RFPLC_TX_DC_Q, tmp, q_mag);
    REG_FIELD_SET(SW_RFPLC_TX_DC, tmp, on_off);
    RFPLC_GENERAL_WRITE_REG(CFG_RFPLC_DBG_CFG1_ADDR, tmp);

    tmp = 0;
    REG_FIELD_SET(SW_RFPLC_FORCE_TX, tmp, on_off);
    RFPLC_GENERAL_WRITE_REG(CFG_RFPLC_DBG_CFG0_ADDR, tmp);

    tmp = RFPLC_GENERAL_READ_REG(CFG_RFPLC_DBG_CFG2_ADDR);
    REG_FIELD_SET(SW_RFPLC_TX_TXNRX, tmp, on_off);
    REG_FIELD_SET(SW_RFPLC_TX_ENABLE, tmp, on_off);
    RFPLC_GENERAL_WRITE_REG(CFG_RFPLC_DBG_CFG2_ADDR, tmp);
}

void mac_rf_tx_tone(uint32_t on_off, uint32_t tone_num, uint32_t tone_att)
{
    /* clear rfplc contrl */
    RFPLC_GENERAL_WRITE_REG(CFG_RFPLC_DBG_CFG0_ADDR, 0);

    uint32_t tmp = RFPLC_GENERAL_READ_REG(CFG_RFPLC_DBG_CFG0_ADDR);
    REG_FIELD_SET(SW_RFPLC_TONE_CFG_EN, tmp, on_off);
    REG_FIELD_SET(SW_RFPLC_TONE_0_ATTEN, tmp, tone_att);
    REG_FIELD_SET(SW_RFPLC_TONE_0_CFG_NUM, tmp, tone_num);
    RFPLC_GENERAL_WRITE_REG(CFG_RFPLC_DBG_CFG0_ADDR, tmp);

    tmp = RFPLC_GENERAL_READ_REG(CFG_RFPLC_DBG_CFG0_ADDR);
    REG_FIELD_SET(SW_RFPLC_FORCE_TX, tmp, on_off);
    RFPLC_GENERAL_WRITE_REG(CFG_RFPLC_DBG_CFG0_ADDR, tmp);

    tmp = RFPLC_GENERAL_READ_REG(CFG_RFPLC_DBG_CFG2_ADDR);
    REG_FIELD_SET(SW_RFPLC_TX_TXNRX, tmp, on_off);
    REG_FIELD_SET(SW_RFPLC_TX_ENABLE, tmp, on_off);
    RFPLC_GENERAL_WRITE_REG(CFG_RFPLC_DBG_CFG2_ADDR, tmp);
}

void mac_rf_set_tx_tone_para(uint32_t on_off, uint32_t rf_option,
    uint32_t tone_num, uint32_t tone_att)
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_TX_TONE_CTL_ADDR);
    REG_FIELD_SET(RF_MAC_TX_TONE_ON_OFF, tmp, on_off);
    REG_FIELD_SET(RF_MAC_TX_TONE_OPTION, tmp, rf_option);
    REG_FIELD_SET(RF_MAC_TX_TONE_NUM, tmp, tone_num);
    REG_FIELD_SET(RF_MAC_TX_TONE_ATT, tmp, tone_att);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_TX_TONE_CTL_ADDR, tmp);
}

void mac_rf_get_tx_tone_para(uint32_t *on_off, uint32_t *rf_option,
    uint32_t *tone_num, uint32_t *tone_att)
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_TX_TONE_CTL_ADDR);
    *on_off = REG_FIELD_GET(RF_MAC_TX_TONE_ON_OFF, tmp);
    *rf_option = REG_FIELD_GET(RF_MAC_TX_TONE_OPTION, tmp);
    *tone_num = REG_FIELD_GET(RF_MAC_TX_TONE_NUM, tmp);
    *tone_att = REG_FIELD_GET(RF_MAC_TX_TONE_ATT, tmp);
}

void mac_rf_set_tx_tone_freq(uint32_t freq)
{
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_TX_TONE_FREQ_ADDR, freq);
}

uint32_t mac_rf_get_tx_tone_freq()
{
    return RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_TX_TONE_FREQ_ADDR);
}

void mac_rf_set_tx_tone_status(uint32_t value)
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_SPI_STATUS_ADDR);
    REG_FIELD_SET(RF_MAC_TX_TONE_STS, tmp, value);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_SPI_STATUS_ADDR, tmp);
}

uint32_t mac_rf_get_tx_tone_status()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_SPI_STATUS_ADDR);
    return REG_FIELD_GET(RF_MAC_TX_TONE_STS, tmp);
}

void mac_rf_set_wphy_ppm(int16_t ppm_err)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_SYNC_PPM_ADDR);
    REG_FIELD_SET(RF_MAC_SET_PPM, tmp, (uint16_t)ppm_err);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_SYNC_PPM_ADDR, tmp);
}

int16_t mac_rf_get_wphy_ppm()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_SYNC_PPM_ADDR);
    return (int16_t)REG_FIELD_GET(RF_MAC_SET_PPM, tmp);
}

void mac_rf_set_pb_hdr_to_buf(uint32_t value)
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_CERT_INFO_ADDR);
    REG_FIELD_SET(RF_MAC_CERT_PB_HDR_TO_BUF, tmp, value);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_CERT_INFO_ADDR, tmp);
}

uint32_t mac_rf_get_pb_hdr_to_buf()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_CERT_INFO_ADDR);
    return REG_FIELD_GET(RF_MAC_CERT_PB_HDR_TO_BUF, tmp);
}

void mac_rf_set_bb_ps_idle(uint32_t ps_on)
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_CERT_INFO_ADDR);
    REG_FIELD_SET(RF_MAC_SET_PS_IDLE, tmp, ps_on);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_CERT_INFO_ADDR, tmp);
}

uint32_t mac_rf_get_bb_ps_idle()
{
    uint32_t tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_CERT_INFO_ADDR);
    return REG_FIELD_GET(RF_MAC_SET_PS_IDLE, tmp);
}

void mac_rf_set_target_tx_power(int8_t dbm)
{
    uint32_t tmp;
    int8_t min_pwr, max_pwr, def_pwr;
    phy_rf_get_power(&min_pwr, &max_pwr, &def_pwr, NULL);

    if (dbm == RF_TX_PWR_INVALID) {
        /* restore the default tx power */
        dbm = def_pwr;
    } else if (dbm >= max_pwr) {
        dbm = max_pwr;
    } else {
        dbm = max(dbm, min_pwr);
    }
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    REG_FIELD_SET(RF_MAC_TARGET_TX_PWR_ENA, tmp, 1);
    REG_FIELD_SET(RF_MAC_TARGET_TX_PWR, tmp, (uint8_t)dbm);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR, tmp);
}

uint32_t mac_rf_get_target_tx_power(int8_t *pwr)
{
    uint32_t tmp;

    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    if (REG_FIELD_GET(RF_MAC_TARGET_TX_PWR_ENA, tmp) && pwr) {
        *pwr = (int8_t)REG_FIELD_GET(RF_MAC_TARGET_TX_PWR, tmp);
        return ERR_OK;
    }

    return ERR_FAIL;
}

void mac_rf_disable_pa(uint32_t is_disable)
{
    uint32_t tmp = RFPLC_GENERAL_READ_REG(CFG_RFPLC_FCLK_CTRL_ADDR);
    REG_FIELD_SET(RFPLC_WAFE_PD, tmp, !!is_disable);
    RFPLC_GENERAL_WRITE_REG(CFG_RFPLC_FCLK_CTRL_ADDR, tmp);
}

uint32_t mac_rf_is_pa_disable()
{
    uint32_t tmp = RFPLC_GENERAL_READ_REG(CFG_RFPLC_FCLK_CTRL_ADDR);
    return REG_FIELD_GET(RFPLC_WAFE_PD, tmp);
}

void mac_rf_set_proto(uint32_t proto)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    REG_FIELD_SET(RF_MAC_PROTO, tmp, proto);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR, tmp);
}

uint32_t mac_rf_get_proto()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    return REG_FIELD_GET(RF_MAC_PROTO, tmp);
}

void mac_rf_set_band_sel(uint32_t band_sel)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    REG_FIELD_SET(RF_MAC_BAND_SEL, tmp, band_sel);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR, tmp);
}

uint32_t mac_rf_get_band_sel()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    return REG_FIELD_GET(RF_MAC_BAND_SEL, tmp);
}

/* config set rf rx dc clibration enable */
void mac_rf_set_rx_dc_loopback_clibr_en(uint32_t enable)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    REG_FIELD_SET(RF_RX_DC_LOOPBACK_CALI_EN, tmp, enable);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR, tmp);
}

/* config get rf rx dc clibration enable */
uint32_t mac_rf_get_rx_dc_loopback_clibr_en()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    return REG_FIELD_GET(RF_RX_DC_LOOPBACK_CALI_EN, tmp);
}

/* config set rf tx dc clibration enable */
void mac_rf_set_tx_dc_loopback_clibr_en(uint32_t enable)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    REG_FIELD_SET(RF_TX_DC_LOOPBACK_CALI_EN, tmp, enable);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR, tmp);
}

/* config get rf tx dc clibration enable */
uint32_t mac_rf_get_tx_dc_loopback_clibr_en()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    return REG_FIELD_GET(RF_TX_DC_LOOPBACK_CALI_EN, tmp);
}

/* config set rf rx dc clibration flag */
void mac_rf_set_rx_dc_loopback_clibr_flag(uint32_t value)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_BB_CPU_STS_ADDR);
    REG_FIELD_SET(RF_RX_DC_LOOPBACK_CALI_FLAG, tmp, value);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_BB_CPU_STS_ADDR, tmp);
}

/* config get rf rx dc clibration flag */
uint32_t mac_rf_get_rx_dc_loopback_clibr_flag()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_BB_CPU_STS_ADDR);
    return REG_FIELD_GET(RF_RX_DC_LOOPBACK_CALI_FLAG, tmp);
}

void mac_rf_set_auto_rxdc_iq_value(uint8_t i_value, uint8_t q_value)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_AUTO_RXDC_CALI_ADDR);
    REG_FIELD_SET(RF_PHY_RECORD_RXDC_I, tmp, i_value);
    REG_FIELD_SET(RF_PHY_RECORD_RXDC_Q, tmp, q_value);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_AUTO_RXDC_CALI_ADDR, tmp);
}

void mac_rf_get_auto_rxdc_iq_value(uint8_t *i_value, uint8_t *q_value)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_AUTO_RXDC_CALI_ADDR);
    *i_value = REG_FIELD_GET(RF_PHY_RECORD_RXDC_I, tmp);
    *q_value = REG_FIELD_GET(RF_PHY_RECORD_RXDC_Q, tmp);
}

void mac_rf_set_rf_in(uint8_t in)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI1_ADDR);
    REG_FIELD_SET(CFG_RF_MAC_TO_WPHY_RF_IN, tmp, !!in);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_CALI1_ADDR, tmp);
}

uint8_t mac_rf_is_rf_in(void)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_CALI1_ADDR);
    return REG_FIELD_GET(CFG_RF_MAC_TO_WPHY_RF_IN, tmp);
}

void mac_rf_set_sta_sel(uint8_t sta_sel)
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    REG_FIELD_SET(RF_MAC_ROLE_STA_SEL, tmp, sta_sel);
    RF_MAX_CUS_WRITE_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR, tmp);
}

uint32_t mac_rf_is_sta()
{
    uint32_t tmp;
    tmp = RF_MAX_CUS_READ_REG(CFG_RF_MAC_TO_WPHY_PARAM_ADDR);
    return REG_FIELD_GET(RF_MAC_ROLE_STA_SEL, tmp);
}

#endif /* HW_PLATFORM >= HW_PLATFORM_FPGA */