/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/
#include "hw_reg_api.h"
#include "iot_config.h"
#include "phy_bb.h"
#include "phy_dfe_reg.h"
#include "phy_rxtd_reg.h"
#include "granite_reg.h"
#include "hw_tonemask.h"
#include "iot_io.h"
#include "iot_errno_api.h"
#include "mac_sys_reg.h"
#include "os_mem.h"
#include "hw_phy_api.h"
#include "phy_ana.h"
#include "phy_phase.h"
#include "iot_share_task.h"
#include "math_log10.h"
#include "phy_data.h"
#include "hw_phy_api.h"
#include "phy_perf.h"
#include "math_log10.h"
#include "phy_dump_hw.h"
#if HW_PLATFORM >= HW_PLATFORM_FPGA
#include "phy_tools.h"
#include "phy_ada_dump.h"
#endif


void phy_fft_dump_prepare()
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;
    uint32_t fft_loop = 1;

    /* config det tone */
    phy_rxfd_rate0_det(0, 1535);
    phy_rxfd_rate1_det(0, 1535);

    /* tone enable  */
    phy_dfe_tone_cfg(1,0,0);

    /* force inte rx state */
    phy_txrx_ovr_set(1,1);

    /* disable packet detect timeout */
    phy_pkt_time_out_disable(true);

    /* bypass dc blocker */
    tmp = PHY_DFE_READ_REG(CFG_BB_DC_BLK_STAGE_DLY_ADDR);
    REG_FIELD_SET(SW_DC_BLK_BYPASS, tmp, 1);
    PHY_DFE_WRITE_REG(CFG_BB_DC_BLK_STAGE_DLY_ADDR, tmp);

    /* disable adj req and sat */
    phy_agc_sat_adj_set(1,1);

    tmp = PHY_DFE_READ_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR);
    REG_FIELD_SET(SW_LOOPBACK_EN, tmp, 1);
    PHY_DFE_WRITE_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR, tmp);

    /* en adc and rx, disable dac and tx */
    phy_ana_tx_en(false);
    phy_ana_rx_en(true);
    phy_ana_enlic_en(PHY_ENLIC_TXRX_RX);

    /* trig fft */
    tmp = PHY_DFE_READ_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR);
    REG_FIELD_SET(SW_LOOP_FFT_CYCLE, tmp, fft_loop);
    REG_FIELD_SET(SW_LOOP_FFT_START, tmp, 1);
    PHY_DFE_WRITE_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR, tmp);
#endif
}

void phy_increase_tgt_pwr(uint32_t spur_exist)
{
    (void)spur_exist;
}