/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/

#ifndef __SRAM_H
#define __SRAM_H

#ifdef __cplusplus
extern "C" {
#endif

/**
  * @brief  HAL Status structures definition
  */
typedef enum
{
    HAL_SRAM_OK       = 0x00U,
    HAL_SRAM_ERROR    = 0x01U,
    HAL_SRAM_BUSY     = 0x02U,
    HAL_SRAM_TIMEOUT  = 0x03U,
    HAL_SRAM_NOT_SUPPORTED = 0x04U
} sram_rt_sts_t;

uint8_t sram_qspi_init(void);
bool_t sram_qspi_is_busy(void);
uint8_t sram_qspi_write(uint8_t* data, uint32_t wt_addr, uint32_t size);
uint8_t sram_qspi_quad_write(uint8_t* data, uint32_t wt_addr, uint32_t size);
uint8_t sram_qspi_erase_chip(void);
uint8_t sram_qspi_read(uint8_t* data, uint32_t read_addr, uint32_t size);
uint8_t sram_qspi_quad_read(uint8_t* data, uint32_t read_addr, uint32_t size);
uint8_t sram_qspi_enter(void);
uint8_t sram_qspi_exit(void);


#ifdef __cplusplus
}
#endif

#endif