#ifndef __GD25Q32C_H
#define __GD25Q32C_H

#define WRITE_EN_CMD                0x06
#define WRITE_DIS_CMD               0x04
#define VOLATILE_SR_WR_EN_CMD       0x50
#define READ_STS_REG1_CMD           0x05
#define READ_STS_REG2_CMD           0x35
//#define READ_STS_REG3_CMD           0x15
#define WRITE_STS_REG1_CMD          0x01
#define WRITE_STS_REG2_CMD          0x31
//#define WRITE_STS_REG3_CMD          0x11
#define READ_DATA_CMD               0x03
#define FAST_READ_CMD               0x0B
#define DUAL_OUTPUT_FAST_RD_CMD     0x3B
#define DUAL_IO_FAST_RD_CMD         0xBB
#define QUAD_OUTPUT_FAST_RD_CMD     0x6B
#define QUAD_IO_FAST_RD_CMD         0xEB
#define QUAD_IO_WORD_FAST_RD_CMD    0xE7
#define PAGE_PROGRAM_CMD            0x02
#define QUAD_PAGE_PROGRAM_CMD       0x32
//#define FAST_PAGE_PROGRAM_CMD       0xF2
#define PAGE_ERASE_CMD              0x81
#define SECTOR_ERASE_CMD            0x20
//#define BLOCK_ERASE_32K_CMD         0x52
#define BLOCK_ERASE_64K_CMD         0xD8
#define CHIP_ERASE_CMD              0xC7    /*0x60*/
#define RESET_EN_CMD                0x66
#define RESET_CMD                   0x99
//#define SET_BURST_WITH_WRAP_CMD     0x77
#define PROGRAM_ERASE_SUSPEND_CMD   0x75
#define PROGRAM_ERASE_RESUME_CMD    0x7A
//#define RELEASE_FROM_DEEP_RD_ID_CMD 0xAB
//#define RELEASE_FROM_DEEP_CMD       0xAB
//#define DEEP_PWR_DN_CMD             0xB9
#define MANU_DEV_ID_CMD             0x90
#define MANU_DEV_ID_DUAL_IO_CMD     0x92
#define MANU_DEV_ID_QUAD_IO_CMD     0x94
#define READ_ID_CMD                 0x9F
//#define HIGH_PERF_MODE_CMD          0xA3
#define READ_DISCOVERY_PARA_CMD     0x5A
//#define ERASE_SECURITY_REG_CMD      0x44
//#define PROGRAM_SECURITY_REG_CMD    0x42
//#define READ_SECURITY_REG_CMD       0x48
#define READ_UNIQ_ID_CMD            0x4B

#define STS_WIP_BIT_S0              0x01
#define STS_WEL_BIT_S1              0x02
#define QUAD_ENA_BIT_S9             0x02
#define STS_SUS2_BIT_S10            0x04
#define STS_SUS1_BIT_S15            0x80
#define ADDR_DEFAULT_VAL_ZERO       0x00

#define PAGE_PROGRAM_MASK           0xFF
#define SECTOR_ERASE_MASK           0xFFF
//#define BLOCK_ERASE_32K_MASK        0x1FFFF
#define BLOCK_ERASE_64K_MASK        0xFFFF

#define P25Q16_32LE_SFDP            0xF1 /* PUYA 2/4MB 55nm SFDP */
#define P25Q16_32SL_SFDP            0xF9 /* PUYA 2/4MB 40nm SFDP */

#endif